1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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40#include "Global.hh"
41#include "RubyConfig.hh"
42#include "Consumer.hh"
43#include "CacheRequestType.hh"
44#include "AccessModeType.hh"
45#include "GenericMachineType.hh"
46#include "PrefetchBit.hh"
47#include "Map.hh"
48
49class DataBlock;
50class AbstractChip;
51class CacheMsg;
52class Address;
53class MachineID;
54
55class Sequencer : public Consumer {

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103 Address getRequestPhysicalAddress(const Address & lineaddr);
104 // returns whether a request is a prefetch request
105 bool isPrefetchRequest(const Address & lineaddr);
106
107 //notifies driver of debug print
108 void printDebug();
109
110 // called by Tester or Simics
111 void makeRequest(const CacheMsg& request);
112 bool doRequest(const CacheMsg& request);
113 void issueRequest(const CacheMsg& request);
114 bool isReady(const CacheMsg& request) const;
115 bool empty() const;
116 void resetRequestTime(const Address& addr, int thread);
117 Address getLogicalAddressOfRequest(Address address, int thread);
118 AccessModeType getAccessModeOfRequest(Address address, int thread);
119 //uint64 getSequenceNumberOfRequest(Address addr, int thread);
120
121 void print(ostream& out) const;
122 void checkCoherence(const Address& address);

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