1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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61 public:
62 typedef RubySequencerParams Params;
63 Sequencer(const Params *);
64 ~Sequencer();
65
66 // Public Methods
67 void wakeup(); // Used only for deadlock detection
68 void printProgress(std::ostream& out) const;
69 void resetStats();
70 void collateStats();
71 void regStats();
72
73 void writeCallback(const Address& address,
74 DataBlock& data,
75 const bool externalHit = false,
76 const MachineType mach = MachineType_NUM,
77 const Cycles initialRequestTime = Cycles(0),
78 const Cycles forwardRequestTime = Cycles(0),
79 const Cycles firstResponseTime = Cycles(0));

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92
93 bool isDeadlockEventScheduled() const
94 { return deadlockCheckEvent.scheduled(); }
95
96 void descheduleDeadlockEvent()
97 { deschedule(deadlockCheckEvent); }
98
99 void print(std::ostream& out) const;
100 void checkCoherence(const Address& address);
101
102 void markRemoved();
103 void removeRequest(SequencerRequest* request);
104 void evictionCallback(const Address& address);
105 void invalidateSC(const Address& address);
106
107 void recordRequestType(SequencerRequestType requestType);
108 Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
109
110 Stats::Histogram& getLatencyHist() { return m_latencyHist; }
111 Stats::Histogram& getTypeLatencyHist(uint32_t t)
112 { return *m_typeLatencyHist[t]; }
113
114 Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; }
115 Stats::Histogram& getHitTypeLatencyHist(uint32_t t)
116 { return *m_hitTypeLatencyHist[t]; }
117
118 Stats::Histogram& getHitMachLatencyHist(uint32_t t)
119 { return *m_hitMachLatencyHist[t]; }
120
121 Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
122 { return *m_hitTypeMachLatencyHist[r][t]; }
123
124 Stats::Histogram& getMissLatencyHist()
125 { return m_missLatencyHist; }
126 Stats::Histogram& getMissTypeLatencyHist(uint32_t t)
127 { return *m_missTypeLatencyHist[t]; }
128
129 Stats::Histogram& getMissMachLatencyHist(uint32_t t) const
130 { return *m_missMachLatencyHist[t]; }
131
132 Stats::Histogram&
133 getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
134 { return *m_missTypeMachLatencyHist[r][t]; }
135
136 Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const
137 { return *m_IssueToInitialDelayHist[t]; }
138
139 Stats::Histogram&
140 getInitialToForwardDelayHist(const MachineType t) const
141 { return *m_InitialToForwardDelayHist[t]; }
142
143 Stats::Histogram&
144 getForwardRequestToFirstResponseHist(const MachineType t) const
145 { return *m_ForwardToFirstResponseDelayHist[t]; }
146
147 Stats::Histogram&
148 getFirstResponseToCompletionDelayHist(const MachineType t) const
149 { return *m_FirstResponseToCompletionDelayHist[t]; }
150
151 Stats::Counter getIncompleteTimes(const MachineType t) const
152 { return m_IncompleteTimes[t]; }
153
154 private:
155 void issueRequest(PacketPtr pkt, RubyRequestType type);
156
157 void hitCallback(SequencerRequest* request, DataBlock& data,
158 bool llscSuccess,
159 const MachineType mach, const bool externalHit,

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184
185 typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
186 RequestTable m_writeRequestTable;
187 RequestTable m_readRequestTable;
188 // Global outstanding request count, across all request tables
189 int m_outstanding_count;
190 bool m_deadlock_check_scheduled;
191
192 //! Counters for recording aliasing information.
193 Stats::Scalar m_store_waiting_on_load;
194 Stats::Scalar m_store_waiting_on_store;
195 Stats::Scalar m_load_waiting_on_store;
196 Stats::Scalar m_load_waiting_on_load;
197
198 bool m_usingNetworkTester;
199
200 //! Histogram for number of outstanding requests per cycle.
201 Stats::Histogram m_outstandReqHist;
202
203 //! Histogram for holding latency profile of all requests.
204 Stats::Histogram m_latencyHist;
205 std::vector<Stats::Histogram *> m_typeLatencyHist;
206
207 //! Histogram for holding latency profile of all requests that
208 //! hit in the controller connected to this sequencer.
209 Stats::Histogram m_hitLatencyHist;
210 std::vector<Stats::Histogram *> m_hitTypeLatencyHist;
211
212 //! Histograms for profiling the latencies for requests that
213 //! did not required external messages.
214 std::vector<Stats::Histogram *> m_hitMachLatencyHist;
215 std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist;
216
217 //! Histogram for holding latency profile of all requests that
218 //! miss in the controller connected to this sequencer.
219 Stats::Histogram m_missLatencyHist;
220 std::vector<Stats::Histogram *> m_missTypeLatencyHist;
221
222 //! Histograms for profiling the latencies for requests that
223 //! required external messages.
224 std::vector<Stats::Histogram *> m_missMachLatencyHist;
225 std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist;
226
227 //! Histograms for recording the breakdown of miss latency
228 std::vector<Stats::Histogram *> m_IssueToInitialDelayHist;
229 std::vector<Stats::Histogram *> m_InitialToForwardDelayHist;
230 std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist;
231 std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist;
232 std::vector<Stats::Counter> m_IncompleteTimes;
233
234
235 class SequencerWakeupEvent : public Event
236 {
237 private:
238 Sequencer *m_sequencer_ptr;
239
240 public:

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