Sequencer.cc (9501:378817542866) Sequencer.cc (9507:d2ab6d889fc7)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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354void
355Sequencer::writeCallback(const Address& address, DataBlock& data)
356{
357 writeCallback(address, GenericMachineType_NULL, data);
358}
359
360void
361Sequencer::writeCallback(const Address& address,
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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354void
355Sequencer::writeCallback(const Address& address, DataBlock& data)
356{
357 writeCallback(address, GenericMachineType_NULL, data);
358}
359
360void
361Sequencer::writeCallback(const Address& address,
362 GenericMachineType mach,
362 GenericMachineType mach,
363 DataBlock& data)
364{
363 DataBlock& data)
364{
365 writeCallback(address, mach, data, 0, 0, 0);
365 writeCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
366}
367
368void
369Sequencer::writeCallback(const Address& address,
366}
367
368void
369Sequencer::writeCallback(const Address& address,
370 GenericMachineType mach,
370 GenericMachineType mach,
371 DataBlock& data,
371 DataBlock& data,
372 Time initialRequestTime,
373 Time forwardRequestTime,
374 Time firstResponseTime)
372 Cycles initialRequestTime,
373 Cycles forwardRequestTime,
374 Cycles firstResponseTime)
375{
376 assert(address == line_address(address));
377 assert(m_writeRequestTable.count(line_address(address)));
378
379 RequestTable::iterator i = m_writeRequestTable.find(address);
380 assert(i != m_writeRequestTable.end());
381 SequencerRequest* request = i->second;
382

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405 success = handleLlsc(address, request);
406
407 if (request->m_type == RubyRequestType_Locked_RMW_Read) {
408 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
409 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
410 m_controller->unblock(address);
411 }
412
375{
376 assert(address == line_address(address));
377 assert(m_writeRequestTable.count(line_address(address)));
378
379 RequestTable::iterator i = m_writeRequestTable.find(address);
380 assert(i != m_writeRequestTable.end());
381 SequencerRequest* request = i->second;
382

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405 success = handleLlsc(address, request);
406
407 if (request->m_type == RubyRequestType_Locked_RMW_Read) {
408 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
409 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
410 m_controller->unblock(address);
411 }
412
413 hitCallback(request, mach, data, success,
413 hitCallback(request, mach, data, success,
414 initialRequestTime, forwardRequestTime, firstResponseTime);
415}
416
417void
418Sequencer::readCallback(const Address& address, DataBlock& data)
419{
420 readCallback(address, GenericMachineType_NULL, data);
421}
422
423void
424Sequencer::readCallback(const Address& address,
425 GenericMachineType mach,
426 DataBlock& data)
427{
414 initialRequestTime, forwardRequestTime, firstResponseTime);
415}
416
417void
418Sequencer::readCallback(const Address& address, DataBlock& data)
419{
420 readCallback(address, GenericMachineType_NULL, data);
421}
422
423void
424Sequencer::readCallback(const Address& address,
425 GenericMachineType mach,
426 DataBlock& data)
427{
428 readCallback(address, mach, data, 0, 0, 0);
428 readCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
429}
430
431void
432Sequencer::readCallback(const Address& address,
433 GenericMachineType mach,
434 DataBlock& data,
429}
430
431void
432Sequencer::readCallback(const Address& address,
433 GenericMachineType mach,
434 DataBlock& data,
435 Time initialRequestTime,
436 Time forwardRequestTime,
437 Time firstResponseTime)
435 Cycles initialRequestTime,
436 Cycles forwardRequestTime,
437 Cycles firstResponseTime)
438{
439 assert(address == line_address(address));
440 assert(m_readRequestTable.count(line_address(address)));
441
442 RequestTable::iterator i = m_readRequestTable.find(address);
443 assert(i != m_readRequestTable.end());
444 SequencerRequest* request = i->second;
445
446 m_readRequestTable.erase(i);
447 markRemoved();
448
449 assert((request->m_type == RubyRequestType_LD) ||
450 (request->m_type == RubyRequestType_IFETCH));
451
438{
439 assert(address == line_address(address));
440 assert(m_readRequestTable.count(line_address(address)));
441
442 RequestTable::iterator i = m_readRequestTable.find(address);
443 assert(i != m_readRequestTable.end());
444 SequencerRequest* request = i->second;
445
446 m_readRequestTable.erase(i);
447 markRemoved();
448
449 assert((request->m_type == RubyRequestType_LD) ||
450 (request->m_type == RubyRequestType_IFETCH));
451
452 hitCallback(request, mach, data, true,
452 hitCallback(request, mach, data, true,
453 initialRequestTime, forwardRequestTime, firstResponseTime);
454}
455
456void
457Sequencer::hitCallback(SequencerRequest* srequest,
458 GenericMachineType mach,
459 DataBlock& data,
460 bool success,
453 initialRequestTime, forwardRequestTime, firstResponseTime);
454}
455
456void
457Sequencer::hitCallback(SequencerRequest* srequest,
458 GenericMachineType mach,
459 DataBlock& data,
460 bool success,
461 Time initialRequestTime,
462 Time forwardRequestTime,
463 Time firstResponseTime)
461 Cycles initialRequestTime,
462 Cycles forwardRequestTime,
463 Cycles firstResponseTime)
464{
465 PacketPtr pkt = srequest->pkt;
466 Address request_address(pkt->getAddr());
467 Address request_line_address(pkt->getAddr());
468 request_line_address.makeLineAddress();
469 RubyRequestType type = srequest->m_type;
464{
465 PacketPtr pkt = srequest->pkt;
466 Address request_address(pkt->getAddr());
467 Address request_line_address(pkt->getAddr());
468 request_line_address.makeLineAddress();
469 RubyRequestType type = srequest->m_type;
470 Time issued_time = srequest->issue_time;
470 Cycles issued_time = srequest->issue_time;
471
472 // Set this cache entry to the most recently used
473 if (type == RubyRequestType_IFETCH) {
474 m_instCache_ptr->setMRU(request_line_address);
475 } else {
476 m_dataCache_ptr->setMRU(request_line_address);
477 }
478
479 assert(curCycle() >= issued_time);
471
472 // Set this cache entry to the most recently used
473 if (type == RubyRequestType_IFETCH) {
474 m_instCache_ptr->setMRU(request_line_address);
475 } else {
476 m_dataCache_ptr->setMRU(request_line_address);
477 }
478
479 assert(curCycle() >= issued_time);
480 Time miss_latency = curCycle() - issued_time;
480 Cycles miss_latency = curCycle() - issued_time;
481
482 // Profile the miss latency for all non-zero demand misses
483 if (miss_latency != 0) {
484 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
485
486 if (mach == GenericMachineType_L1Cache_wCC) {
487 g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
488 initialRequestTime, forwardRequestTime,

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482 // Profile the miss latency for all non-zero demand misses
483 if (miss_latency != 0) {
484 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
485
486 if (mach == GenericMachineType_L1Cache_wCC) {
487 g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
488 initialRequestTime, forwardRequestTime,

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