Sequencer.cc (9342:6fec8f26e56d) | Sequencer.cc (9465:4ae4f3f4b870) |
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1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 74 unchanged lines hidden (view full) --- 83} 84 85void 86Sequencer::wakeup() 87{ 88 assert(getDrainState() != Drainable::Draining); 89 90 // Check for deadlock of any of the requests | 1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 74 unchanged lines hidden (view full) --- 83} 84 85void 86Sequencer::wakeup() 87{ 88 assert(getDrainState() != Drainable::Draining); 89 90 // Check for deadlock of any of the requests |
91 Time current_time = g_system_ptr->getTime(); | 91 Time current_time = curCycle(); |
92 93 // Check across all outstanding requests 94 int total_outstanding = 0; 95 96 RequestTable::iterator read = m_readRequestTable.begin(); 97 RequestTable::iterator read_end = m_readRequestTable.end(); 98 for (; read != read_end; ++read) { 99 SequencerRequest* request = read->second; --- 25 unchanged lines hidden (view full) --- 125 126 total_outstanding += m_writeRequestTable.size(); 127 total_outstanding += m_readRequestTable.size(); 128 129 assert(m_outstanding_count == total_outstanding); 130 131 if (m_outstanding_count > 0) { 132 // If there are still outstanding requests, keep checking | 92 93 // Check across all outstanding requests 94 int total_outstanding = 0; 95 96 RequestTable::iterator read = m_readRequestTable.begin(); 97 RequestTable::iterator read_end = m_readRequestTable.end(); 98 for (; read != read_end; ++read) { 99 SequencerRequest* request = read->second; --- 25 unchanged lines hidden (view full) --- 125 126 total_outstanding += m_writeRequestTable.size(); 127 total_outstanding += m_readRequestTable.size(); 128 129 assert(m_outstanding_count == total_outstanding); 130 131 if (m_outstanding_count > 0) { 132 // If there are still outstanding requests, keep checking |
133 schedule(deadlockCheckEvent, 134 g_system_ptr->clockPeriod() * m_deadlock_threshold + curTick()); | 133 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); |
135 } 136} 137 138void 139Sequencer::printStats(ostream & out) const 140{ 141 out << "Sequencer: " << m_name << endl 142 << " store_waiting_on_load_cycles: " --- 63 unchanged lines hidden (view full) --- 206Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) 207{ 208 assert(m_outstanding_count == 209 (m_writeRequestTable.size() + m_readRequestTable.size())); 210 211 // See if we should schedule a deadlock check 212 if (!deadlockCheckEvent.scheduled() && 213 getDrainState() != Drainable::Draining) { | 134 } 135} 136 137void 138Sequencer::printStats(ostream & out) const 139{ 140 out << "Sequencer: " << m_name << endl 141 << " store_waiting_on_load_cycles: " --- 63 unchanged lines hidden (view full) --- 205Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) 206{ 207 assert(m_outstanding_count == 208 (m_writeRequestTable.size() + m_readRequestTable.size())); 209 210 // See if we should schedule a deadlock check 211 if (!deadlockCheckEvent.scheduled() && 212 getDrainState() != Drainable::Draining) { |
214 schedule(deadlockCheckEvent, 215 g_system_ptr->clockPeriod() * m_deadlock_threshold + curTick()); | 213 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); |
216 } 217 218 Address line_addr(pkt->getAddr()); 219 line_addr.makeLineAddress(); 220 // Create a default entry, mapping the address to NULL, the cast is 221 // there to make gcc 4.4 happy 222 RequestTable::value_type default_entry(line_addr, 223 (SequencerRequest*) NULL); --- 13 unchanged lines hidden (view full) --- 237 m_store_waiting_on_load_cycles++; 238 return RequestStatus_Aliased; 239 } 240 241 pair<RequestTable::iterator, bool> r = 242 m_writeRequestTable.insert(default_entry); 243 if (r.second) { 244 RequestTable::iterator i = r.first; | 214 } 215 216 Address line_addr(pkt->getAddr()); 217 line_addr.makeLineAddress(); 218 // Create a default entry, mapping the address to NULL, the cast is 219 // there to make gcc 4.4 happy 220 RequestTable::value_type default_entry(line_addr, 221 (SequencerRequest*) NULL); --- 13 unchanged lines hidden (view full) --- 235 m_store_waiting_on_load_cycles++; 236 return RequestStatus_Aliased; 237 } 238 239 pair<RequestTable::iterator, bool> r = 240 m_writeRequestTable.insert(default_entry); 241 if (r.second) { 242 RequestTable::iterator i = r.first; |
245 i->second = new SequencerRequest(pkt, request_type, 246 g_system_ptr->getTime()); | 243 i->second = new SequencerRequest(pkt, request_type, curCycle()); |
247 m_outstanding_count++; 248 } else { 249 // There is an outstanding write request for the cache line 250 m_store_waiting_on_store_cycles++; 251 return RequestStatus_Aliased; 252 } 253 } else { 254 // Check if there is any outstanding write request for the same 255 // cache line. 256 if (m_writeRequestTable.count(line_addr) > 0) { 257 m_load_waiting_on_store_cycles++; 258 return RequestStatus_Aliased; 259 } 260 261 pair<RequestTable::iterator, bool> r = 262 m_readRequestTable.insert(default_entry); 263 264 if (r.second) { 265 RequestTable::iterator i = r.first; | 244 m_outstanding_count++; 245 } else { 246 // There is an outstanding write request for the cache line 247 m_store_waiting_on_store_cycles++; 248 return RequestStatus_Aliased; 249 } 250 } else { 251 // Check if there is any outstanding write request for the same 252 // cache line. 253 if (m_writeRequestTable.count(line_addr) > 0) { 254 m_load_waiting_on_store_cycles++; 255 return RequestStatus_Aliased; 256 } 257 258 pair<RequestTable::iterator, bool> r = 259 m_readRequestTable.insert(default_entry); 260 261 if (r.second) { 262 RequestTable::iterator i = r.first; |
266 i->second = new SequencerRequest(pkt, request_type, 267 g_system_ptr->getTime()); | 263 i->second = new SequencerRequest(pkt, request_type, curCycle()); |
268 m_outstanding_count++; 269 } else { 270 // There is an outstanding read request for the cache line 271 m_load_waiting_on_load_cycles++; 272 return RequestStatus_Aliased; 273 } 274 } 275 --- 199 unchanged lines hidden (view full) --- 475 476 // Set this cache entry to the most recently used 477 if (type == RubyRequestType_IFETCH) { 478 m_instCache_ptr->setMRU(request_line_address); 479 } else { 480 m_dataCache_ptr->setMRU(request_line_address); 481 } 482 | 264 m_outstanding_count++; 265 } else { 266 // There is an outstanding read request for the cache line 267 m_load_waiting_on_load_cycles++; 268 return RequestStatus_Aliased; 269 } 270 } 271 --- 199 unchanged lines hidden (view full) --- 471 472 // Set this cache entry to the most recently used 473 if (type == RubyRequestType_IFETCH) { 474 m_instCache_ptr->setMRU(request_line_address); 475 } else { 476 m_dataCache_ptr->setMRU(request_line_address); 477 } 478 |
483 assert(g_system_ptr->getTime() >= issued_time); 484 Time miss_latency = g_system_ptr->getTime() - issued_time; | 479 assert(curCycle() >= issued_time); 480 Time miss_latency = curCycle() - issued_time; |
485 486 // Profile the miss latency for all non-zero demand misses 487 if (miss_latency != 0) { 488 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach); 489 490 if (mach == GenericMachineType_L1Cache_wCC) { 491 g_system_ptr->getProfiler()->missLatencyWcc(issued_time, | 481 482 // Profile the miss latency for all non-zero demand misses 483 if (miss_latency != 0) { 484 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach); 485 486 if (mach == GenericMachineType_L1Cache_wCC) { 487 g_system_ptr->getProfiler()->missLatencyWcc(issued_time, |
492 initialRequestTime, 493 forwardRequestTime, 494 firstResponseTime, 495 g_system_ptr->getTime()); | 488 initialRequestTime, forwardRequestTime, 489 firstResponseTime, curCycle()); |
496 } 497 498 if (mach == GenericMachineType_Directory) { 499 g_system_ptr->getProfiler()->missLatencyDir(issued_time, | 490 } 491 492 if (mach == GenericMachineType_Directory) { 493 g_system_ptr->getProfiler()->missLatencyDir(issued_time, |
500 initialRequestTime, 501 forwardRequestTime, 502 firstResponseTime, 503 g_system_ptr->getTime()); | 494 initialRequestTime, forwardRequestTime, 495 firstResponseTime, curCycle()); |
504 } 505 506 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n", 507 curTick(), m_version, "Seq", 508 success ? "Done" : "SC_Failed", "", "", 509 request_address, miss_latency); 510 } 511 --- 229 unchanged lines hidden --- | 496 } 497 498 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n", 499 curTick(), m_version, "Seq", 500 success ? "Done" : "SC_Failed", "", "", 501 request_address, miss_latency); 502 } 503 --- 229 unchanged lines hidden --- |