Sequencer.cc (8164:b043c0efa024) Sequencer.cc (8165:5955406f7ed0)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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599
600 // TODO: issue hardware prefetches here
601 return RequestStatus_Issued;
602}
603
604void
605Sequencer::issueRequest(const RubyRequest& request)
606{
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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599
600 // TODO: issue hardware prefetches here
601 return RequestStatus_Issued;
602}
603
604void
605Sequencer::issueRequest(const RubyRequest& request)
606{
607 // TODO: get rid of CacheMsg, CacheRequestType, and
607 // TODO: get rid of CacheMsg, RubyRequestType, and
608 // AccessModeTYpe, & have SLICC use RubyRequest and subtypes
609 // natively
608 // AccessModeTYpe, & have SLICC use RubyRequest and subtypes
609 // natively
610 CacheRequestType ctype;
610 RubyRequestType ctype;
611 switch(request.type) {
612 case RubyRequestType_IFETCH:
611 switch(request.type) {
612 case RubyRequestType_IFETCH:
613 ctype = CacheRequestType_IFETCH;
613 ctype = RubyRequestType_IFETCH;
614 break;
615 case RubyRequestType_LD:
614 break;
615 case RubyRequestType_LD:
616 ctype = CacheRequestType_LD;
616 ctype = RubyRequestType_LD;
617 break;
618 case RubyRequestType_ST:
619 case RubyRequestType_RMW_Read:
620 case RubyRequestType_RMW_Write:
621 //
622 // x86 locked instructions are translated to store cache coherence
623 // requests because these requests should always be treated as read
624 // exclusive operations and should leverage any migratory sharing
625 // optimization built into the protocol.
626 //
627 case RubyRequestType_Locked_RMW_Read:
628 case RubyRequestType_Locked_RMW_Write:
617 break;
618 case RubyRequestType_ST:
619 case RubyRequestType_RMW_Read:
620 case RubyRequestType_RMW_Write:
621 //
622 // x86 locked instructions are translated to store cache coherence
623 // requests because these requests should always be treated as read
624 // exclusive operations and should leverage any migratory sharing
625 // optimization built into the protocol.
626 //
627 case RubyRequestType_Locked_RMW_Read:
628 case RubyRequestType_Locked_RMW_Write:
629 ctype = CacheRequestType_ST;
629 ctype = RubyRequestType_ST;
630 break;
631 //
632 // Alpha LL/SC instructions need to be handled carefully by the cache
633 // coherence protocol to ensure they follow the proper semantics. In
634 // particular, by identifying the operations as atomic, the protocol
635 // should understand that migratory sharing optimizations should not be
636 // performed (i.e. a load between the LL and SC should not steal away
637 // exclusive permission).
638 //
639 case RubyRequestType_Load_Linked:
640 case RubyRequestType_Store_Conditional:
630 break;
631 //
632 // Alpha LL/SC instructions need to be handled carefully by the cache
633 // coherence protocol to ensure they follow the proper semantics. In
634 // particular, by identifying the operations as atomic, the protocol
635 // should understand that migratory sharing optimizations should not be
636 // performed (i.e. a load between the LL and SC should not steal away
637 // exclusive permission).
638 //
639 case RubyRequestType_Load_Linked:
640 case RubyRequestType_Store_Conditional:
641 ctype = CacheRequestType_ATOMIC;
641 ctype = RubyRequestType_ATOMIC;
642 break;
643 default:
644 assert(0);
645 }
646
647 RubyAccessMode amtype;
648 switch(request.access_mode){
649 case RubyAccessMode_User:

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680 assert(latency > 0);
681
682 assert(m_mandatory_q_ptr != NULL);
683 m_mandatory_q_ptr->enqueue(msg, latency);
684}
685
686#if 0
687bool
642 break;
643 default:
644 assert(0);
645 }
646
647 RubyAccessMode amtype;
648 switch(request.access_mode){
649 case RubyAccessMode_User:

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680 assert(latency > 0);
681
682 assert(m_mandatory_q_ptr != NULL);
683 m_mandatory_q_ptr->enqueue(msg, latency);
684}
685
686#if 0
687bool
688Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
688Sequencer::tryCacheAccess(const Address& addr, RubyRequestType type,
689 RubyAccessMode access_mode,
690 int size, DataBlock*& data_ptr)
691{
692 CacheMemory *cache =
689 RubyAccessMode access_mode,
690 int size, DataBlock*& data_ptr)
691{
692 CacheMemory *cache =
693 (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
693 (type == RubyRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
694
695 return cache->tryCacheAccess(line_address(addr), type, data_ptr);
696}
697#endif
698
699template <class KEY, class VALUE>
700std::ostream &
701operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)

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695 return cache->tryCacheAccess(line_address(addr), type, data_ptr);
696}
697#endif
698
699template <class KEY, class VALUE>
700std::ostream &
701operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)

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