Sequencer.cc (8092:6782b51ae8a8) Sequencer.cc (8164:b043c0efa024)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 630 unchanged lines hidden (view full) ---

639 case RubyRequestType_Load_Linked:
640 case RubyRequestType_Store_Conditional:
641 ctype = CacheRequestType_ATOMIC;
642 break;
643 default:
644 assert(0);
645 }
646
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 630 unchanged lines hidden (view full) ---

639 case RubyRequestType_Load_Linked:
640 case RubyRequestType_Store_Conditional:
641 ctype = CacheRequestType_ATOMIC;
642 break;
643 default:
644 assert(0);
645 }
646
647 AccessModeType amtype;
647 RubyAccessMode amtype;
648 switch(request.access_mode){
649 case RubyAccessMode_User:
648 switch(request.access_mode){
649 case RubyAccessMode_User:
650 amtype = AccessModeType_UserMode;
650 amtype = RubyAccessMode_User;
651 break;
652 case RubyAccessMode_Supervisor:
651 break;
652 case RubyAccessMode_Supervisor:
653 amtype = AccessModeType_SupervisorMode;
653 amtype = RubyAccessMode_Supervisor;
654 break;
655 case RubyAccessMode_Device:
654 break;
655 case RubyAccessMode_Device:
656 amtype = AccessModeType_UserMode;
656 amtype = RubyAccessMode_User;
657 break;
658 default:
659 assert(0);
660 }
661
662 Address line_addr(request.paddr);
663 line_addr.makeLineAddress();
664 CacheMsg *msg = new CacheMsg(line_addr, Address(request.paddr), ctype,

--- 16 unchanged lines hidden (view full) ---

681
682 assert(m_mandatory_q_ptr != NULL);
683 m_mandatory_q_ptr->enqueue(msg, latency);
684}
685
686#if 0
687bool
688Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
657 break;
658 default:
659 assert(0);
660 }
661
662 Address line_addr(request.paddr);
663 line_addr.makeLineAddress();
664 CacheMsg *msg = new CacheMsg(line_addr, Address(request.paddr), ctype,

--- 16 unchanged lines hidden (view full) ---

681
682 assert(m_mandatory_q_ptr != NULL);
683 m_mandatory_q_ptr->enqueue(msg, latency);
684}
685
686#if 0
687bool
688Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
689 AccessModeType access_mode,
689 RubyAccessMode access_mode,
690 int size, DataBlock*& data_ptr)
691{
692 CacheMemory *cache =
693 (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
694
695 return cache->tryCacheAccess(line_address(addr), type, data_ptr);
696}
697#endif

--- 36 unchanged lines hidden --- 		690 int size, DataBlock*& data_ptr)
691{
692 CacheMemory *cache =
693 (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
694
695 return cache->tryCacheAccess(line_address(addr), type, data_ptr);
696}
697#endif

--- 36 unchanged lines hidden ---