Sequencer.cc (7560:29d5891a96d6) Sequencer.cc (7565:9fc3475e8175)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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352 writeCallback(address, GenericMachineType_NULL, data);
353}
354
355void
356Sequencer::writeCallback(const Address& address,
357 GenericMachineType mach,
358 DataBlock& data)
359{
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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352 writeCallback(address, GenericMachineType_NULL, data);
353}
354
355void
356Sequencer::writeCallback(const Address& address,
357 GenericMachineType mach,
358 DataBlock& data)
359{
360 writeCallback(address, mach, data, 0, 0, 0);
361}
362
363void
364Sequencer::writeCallback(const Address& address,
365 GenericMachineType mach,
366 DataBlock& data,
367 Time initialRequestTime,
368 Time forwardRequestTime,
369 Time firstResponseTime)
370{
360 assert(address == line_address(address));
361 assert(m_writeRequestTable.count(line_address(address)));
362
363 RequestTable::iterator i = m_writeRequestTable.find(address);
364 assert(i != m_writeRequestTable.end());
365 SequencerRequest* request = i->second;
366
367 m_writeRequestTable.erase(i);

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380 bool success = handleLlsc(address, request);
381
382 if (request->ruby_request.type == RubyRequestType_RMW_Read) {
383 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
384 } else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
385 m_controller->unblock(address);
386 }
387
371 assert(address == line_address(address));
372 assert(m_writeRequestTable.count(line_address(address)));
373
374 RequestTable::iterator i = m_writeRequestTable.find(address);
375 assert(i != m_writeRequestTable.end());
376 SequencerRequest* request = i->second;
377
378 m_writeRequestTable.erase(i);

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391 bool success = handleLlsc(address, request);
392
393 if (request->ruby_request.type == RubyRequestType_RMW_Read) {
394 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
395 } else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
396 m_controller->unblock(address);
397 }
398
388 hitCallback(request, mach, data, success);
399 hitCallback(request, mach, data, success,
400 initialRequestTime, forwardRequestTime, firstResponseTime);
389}
390
391void
392Sequencer::readCallback(const Address& address, DataBlock& data)
393{
394 readCallback(address, GenericMachineType_NULL, data);
395}
396
397void
398Sequencer::readCallback(const Address& address,
399 GenericMachineType mach,
400 DataBlock& data)
401{
401}
402
403void
404Sequencer::readCallback(const Address& address, DataBlock& data)
405{
406 readCallback(address, GenericMachineType_NULL, data);
407}
408
409void
410Sequencer::readCallback(const Address& address,
411 GenericMachineType mach,
412 DataBlock& data)
413{
414 readCallback(address, mach, data, 0, 0, 0);
415}
416
417void
418Sequencer::readCallback(const Address& address,
419 GenericMachineType mach,
420 DataBlock& data,
421 Time initialRequestTime,
422 Time forwardRequestTime,
423 Time firstResponseTime)
424{
402 assert(address == line_address(address));
403 assert(m_readRequestTable.count(line_address(address)));
404
405 RequestTable::iterator i = m_readRequestTable.find(address);
406 assert(i != m_readRequestTable.end());
407 SequencerRequest* request = i->second;
408
409 m_readRequestTable.erase(i);
410 markRemoved();
411
412 assert((request->ruby_request.type == RubyRequestType_LD) ||
413 (request->ruby_request.type == RubyRequestType_RMW_Read) ||
414 (request->ruby_request.type == RubyRequestType_IFETCH));
415
425 assert(address == line_address(address));
426 assert(m_readRequestTable.count(line_address(address)));
427
428 RequestTable::iterator i = m_readRequestTable.find(address);
429 assert(i != m_readRequestTable.end());
430 SequencerRequest* request = i->second;
431
432 m_readRequestTable.erase(i);
433 markRemoved();
434
435 assert((request->ruby_request.type == RubyRequestType_LD) ||
436 (request->ruby_request.type == RubyRequestType_RMW_Read) ||
437 (request->ruby_request.type == RubyRequestType_IFETCH));
438
416 hitCallback(request, mach, data, true);
439 hitCallback(request, mach, data, true,
440 initialRequestTime, forwardRequestTime, firstResponseTime);
417}
418
419void
420Sequencer::hitCallback(SequencerRequest* srequest,
421 GenericMachineType mach,
422 DataBlock& data,
441}
442
443void
444Sequencer::hitCallback(SequencerRequest* srequest,
445 GenericMachineType mach,
446 DataBlock& data,
423 bool success)
447 bool success,
448 Time initialRequestTime,
449 Time forwardRequestTime,
450 Time firstResponseTime)
424{
425 const RubyRequest & ruby_request = srequest->ruby_request;
426 Address request_address(ruby_request.paddr);
427 Address request_line_address(ruby_request.paddr);
428 request_line_address.makeLineAddress();
429 RubyRequestType type = ruby_request.type;
430 Time issued_time = srequest->issue_time;
431

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440
441 assert(g_eventQueue_ptr->getTime() >= issued_time);
442 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
443
444 // Profile the miss latency for all non-zero demand misses
445 if (miss_latency != 0) {
446 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
447
451{
452 const RubyRequest & ruby_request = srequest->ruby_request;
453 Address request_address(ruby_request.paddr);
454 Address request_line_address(ruby_request.paddr);
455 request_line_address.makeLineAddress();
456 RubyRequestType type = ruby_request.type;
457 Time issued_time = srequest->issue_time;
458

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467
468 assert(g_eventQueue_ptr->getTime() >= issued_time);
469 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
470
471 // Profile the miss latency for all non-zero demand misses
472 if (miss_latency != 0) {
473 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
474
475 if (mach == GenericMachineType_L1Cache_wCC) {
476 g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
477 initialRequestTime,
478 forwardRequestTime,
479 firstResponseTime,
480 g_eventQueue_ptr->getTime());
481 }
482
483 if (mach == GenericMachineType_Directory) {
484 g_system_ptr->getProfiler()->missLatencyDir(issued_time,
485 initialRequestTime,
486 forwardRequestTime,
487 firstResponseTime,
488 g_eventQueue_ptr->getTime());
489 }
490
448 if (Debug::getProtocolTrace()) {
449 if (success) {
450 g_system_ptr->getProfiler()->
451 profileTransition("Seq", m_version,
452 Address(ruby_request.paddr), "", "Done", "",
453 csprintf("%d cycles", miss_latency));
454 } else {
455 g_system_ptr->getProfiler()->

--- 240 unchanged lines hidden --- 		491 if (Debug::getProtocolTrace()) {
492 if (success) {
493 g_system_ptr->getProfiler()->
494 profileTransition("Seq", m_version,
495 Address(ruby_request.paddr), "", "Done", "",
496 csprintf("%d cycles", miss_latency));
497 } else {
498 g_system_ptr->getProfiler()->

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