Sequencer.cc (7550:7d97cec15818) Sequencer.cc (7560:29d5891a96d6)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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298 m_writeRequestTable.erase(line_addr);
299 } else {
300 m_readRequestTable.erase(line_addr);
301 }
302
303 markRemoved();
304}
305
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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298 m_writeRequestTable.erase(line_addr);
299 } else {
300 m_readRequestTable.erase(line_addr);
301 }
302
303 markRemoved();
304}
305
306void
307Sequencer::handleLlscWrites(const Address& address, SequencerRequest* request)
306bool
307Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
308{
308{
309 //
310 // The success flag indicates whether the LLSC operation was successful.
311 // LL ops will always succeed, but SC may fail if the cache line is no
312 // longer locked.
313 //
314 bool success = true;
309 if (request->ruby_request.type == RubyRequestType_Locked_Write) {
310 if (!m_dataCache_ptr->isLocked(address, m_version)) {
311 //
312 // For failed SC requests, indicate the failure to the cpu by
313 // setting the extra data to zero.
314 //
315 request->ruby_request.pkt->req->setExtraData(0);
315 if (request->ruby_request.type == RubyRequestType_Locked_Write) {
316 if (!m_dataCache_ptr->isLocked(address, m_version)) {
317 //
318 // For failed SC requests, indicate the failure to the cpu by
319 // setting the extra data to zero.
320 //
321 request->ruby_request.pkt->req->setExtraData(0);
322 success = false;
316 } else {
317 //
318 // For successful SC requests, indicate the success to the cpu by
319 // setting the extra data to one.
320 //
321 request->ruby_request.pkt->req->setExtraData(1);
322 }
323 } else {
324 //
325 // For successful SC requests, indicate the success to the cpu by
326 // setting the extra data to one.
327 //
328 request->ruby_request.pkt->req->setExtraData(1);
329 }
330 //
331 // Independent of success, all SC operations must clear the lock
332 //
323 m_dataCache_ptr->clearLocked(address);
324 } else if (request->ruby_request.type == RubyRequestType_Locked_Read) {
325 //
326 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
327 // previously locked cache lines?
328 //
329 m_dataCache_ptr->setLocked(address, m_version);
330 } else if (m_dataCache_ptr->isLocked(address, m_version)) {
331 //
332 // Normal writes should clear the locked address
333 //
334 m_dataCache_ptr->clearLocked(address);
335 }
333 m_dataCache_ptr->clearLocked(address);
334 } else if (request->ruby_request.type == RubyRequestType_Locked_Read) {
335 //
336 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
337 // previously locked cache lines?
338 //
339 m_dataCache_ptr->setLocked(address, m_version);
340 } else if (m_dataCache_ptr->isLocked(address, m_version)) {
341 //
342 // Normal writes should clear the locked address
343 //
344 m_dataCache_ptr->clearLocked(address);
345 }
346 return success;
336}
337
338void
339Sequencer::writeCallback(const Address& address, DataBlock& data)
340{
341 writeCallback(address, GenericMachineType_NULL, data);
342}
343

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361 (request->ruby_request.type == RubyRequestType_RMW_Write) ||
362 (request->ruby_request.type == RubyRequestType_Locked_Read) ||
363 (request->ruby_request.type == RubyRequestType_Locked_Write));
364
365 //
366 // For Alpha, properly handle LL, SC, and write requests with respect to
367 // locked cache blocks.
368 //
347}
348
349void
350Sequencer::writeCallback(const Address& address, DataBlock& data)
351{
352 writeCallback(address, GenericMachineType_NULL, data);
353}
354

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372 (request->ruby_request.type == RubyRequestType_RMW_Write) ||
373 (request->ruby_request.type == RubyRequestType_Locked_Read) ||
374 (request->ruby_request.type == RubyRequestType_Locked_Write));
375
376 //
377 // For Alpha, properly handle LL, SC, and write requests with respect to
378 // locked cache blocks.
379 //
369 handleLlscWrites(address, request);
380 bool success = handleLlsc(address, request);
370
371 if (request->ruby_request.type == RubyRequestType_RMW_Read) {
372 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
373 } else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
374 m_controller->unblock(address);
375 }
376
381
382 if (request->ruby_request.type == RubyRequestType_RMW_Read) {
383 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
384 } else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
385 m_controller->unblock(address);
386 }
387
377 hitCallback(request, mach, data);
388 hitCallback(request, mach, data, success);
378}
379
380void
381Sequencer::readCallback(const Address& address, DataBlock& data)
382{
383 readCallback(address, GenericMachineType_NULL, data);
384}
385

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397
398 m_readRequestTable.erase(i);
399 markRemoved();
400
401 assert((request->ruby_request.type == RubyRequestType_LD) ||
402 (request->ruby_request.type == RubyRequestType_RMW_Read) ||
403 (request->ruby_request.type == RubyRequestType_IFETCH));
404
389}
390
391void
392Sequencer::readCallback(const Address& address, DataBlock& data)
393{
394 readCallback(address, GenericMachineType_NULL, data);
395}
396

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408
409 m_readRequestTable.erase(i);
410 markRemoved();
411
412 assert((request->ruby_request.type == RubyRequestType_LD) ||
413 (request->ruby_request.type == RubyRequestType_RMW_Read) ||
414 (request->ruby_request.type == RubyRequestType_IFETCH));
415
405 hitCallback(request, mach, data);
416 hitCallback(request, mach, data, true);
406}
407
408void
409Sequencer::hitCallback(SequencerRequest* srequest,
410 GenericMachineType mach,
417}
418
419void
420Sequencer::hitCallback(SequencerRequest* srequest,
421 GenericMachineType mach,
411 DataBlock& data)
422 DataBlock& data,
423 bool success)
412{
413 const RubyRequest & ruby_request = srequest->ruby_request;
414 Address request_address(ruby_request.paddr);
415 Address request_line_address(ruby_request.paddr);
416 request_line_address.makeLineAddress();
417 RubyRequestType type = ruby_request.type;
418 Time issued_time = srequest->issue_time;
419

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429 assert(g_eventQueue_ptr->getTime() >= issued_time);
430 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
431
432 // Profile the miss latency for all non-zero demand misses
433 if (miss_latency != 0) {
434 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
435
436 if (Debug::getProtocolTrace()) {
424{
425 const RubyRequest & ruby_request = srequest->ruby_request;
426 Address request_address(ruby_request.paddr);
427 Address request_line_address(ruby_request.paddr);
428 request_line_address.makeLineAddress();
429 RubyRequestType type = ruby_request.type;
430 Time issued_time = srequest->issue_time;
431

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441 assert(g_eventQueue_ptr->getTime() >= issued_time);
442 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
443
444 // Profile the miss latency for all non-zero demand misses
445 if (miss_latency != 0) {
446 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
447
448 if (Debug::getProtocolTrace()) {
437 g_system_ptr->getProfiler()->
438 profileTransition("Seq", m_version,
439 Address(ruby_request.paddr), "", "Done", "",
440 csprintf("%d cycles", miss_latency));
449 if (success) {
450 g_system_ptr->getProfiler()->
451 profileTransition("Seq", m_version,
452 Address(ruby_request.paddr), "", "Done", "",
453 csprintf("%d cycles", miss_latency));
454 } else {
455 g_system_ptr->getProfiler()->
456 profileTransition("Seq", m_version,
457 Address(ruby_request.paddr), "", "SC_Failed", "",
458 csprintf("%d cycles", miss_latency));
459 }
441 }
442 }
443#if 0
444 if (request.getPrefetch() == PrefetchBit_Yes) {
445 return; // Ignore the prefetch
446 }
447#endif
448

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461 }
462#if 0
463 if (request.getPrefetch() == PrefetchBit_Yes) {
464 return; // Ignore the prefetch
465 }
466#endif
467

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