Sequencer.cc (6846:60e0df8086f0) Sequencer.cc (6850:d480ef5b9028)
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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40#include "mem/protocol/Protocol.hh"
41#include "mem/gems_common/Map.hh"
42#include "mem/ruby/buffers/MessageBuffer.hh"
43#include "mem/ruby/slicc_interface/AbstractController.hh"
44
45//Sequencer::Sequencer(int core_id, MessageBuffer* mandatory_q)
46
47#define LLSC_FAIL -2
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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40#include "mem/protocol/Protocol.hh"
41#include "mem/gems_common/Map.hh"
42#include "mem/ruby/buffers/MessageBuffer.hh"
43#include "mem/ruby/slicc_interface/AbstractController.hh"
44
45//Sequencer::Sequencer(int core_id, MessageBuffer* mandatory_q)
46
47#define LLSC_FAIL -2
48
48long int already = 0;
49Sequencer::Sequencer(const string & name)
50 :RubyPort(name)
51{
52}
53
54void Sequencer::init(const vector<string> & argv)
55{
56 m_deadlock_check_scheduled = false;

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349 }
350
351 m_hit_callback(srequest->id);
352 delete srequest;
353}
354
355// Returns true if the sequencer already has a load or store outstanding
356int Sequencer::isReady(const RubyRequest& request) {
49Sequencer::Sequencer(const string & name)
50 :RubyPort(name)
51{
52}
53
54void Sequencer::init(const vector<string> & argv)
55{
56 m_deadlock_check_scheduled = false;

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349 }
350
351 m_hit_callback(srequest->id);
352 delete srequest;
353}
354
355// Returns true if the sequencer already has a load or store outstanding
356int Sequencer::isReady(const RubyRequest& request) {
357 // POLINA: check if we are currently flushing the write buffer, if so Ruby is returned as not ready
358 // to simulate stalling of the front-end
359 // Do we stall all the sequencers? If it is atomic instruction - yes!
360 if (m_outstanding_count >= m_max_outstanding_requests) {
361 return LIBRUBY_BUFFER_FULL;
362 }
363
364 if( m_writeRequestTable.exist(line_address(Address(request.paddr))) ||
365 m_readRequestTable.exist(line_address(Address(request.paddr))) ){
366 //cout << "OUTSTANDING REQUEST EXISTS " << p << " VER " << m_version << endl;
367 //printProgress(cout);

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412void Sequencer::issueRequest(const RubyRequest& request) {
413
414 // TODO: get rid of CacheMsg, CacheRequestType, and AccessModeTYpe, & have SLICC use RubyRequest and subtypes natively
415 CacheRequestType ctype;
416 switch(request.type) {
417 case RubyRequestType_IFETCH:
418 if (m_atomic_reads > 0 && m_atomic_writes == 0) {
419 m_controller->reset_atomics();
357 if (m_outstanding_count >= m_max_outstanding_requests) {
358 return LIBRUBY_BUFFER_FULL;
359 }
360
361 if( m_writeRequestTable.exist(line_address(Address(request.paddr))) ||
362 m_readRequestTable.exist(line_address(Address(request.paddr))) ){
363 //cout << "OUTSTANDING REQUEST EXISTS " << p << " VER " << m_version << endl;
364 //printProgress(cout);

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409void Sequencer::issueRequest(const RubyRequest& request) {
410
411 // TODO: get rid of CacheMsg, CacheRequestType, and AccessModeTYpe, & have SLICC use RubyRequest and subtypes natively
412 CacheRequestType ctype;
413 switch(request.type) {
414 case RubyRequestType_IFETCH:
415 if (m_atomic_reads > 0 && m_atomic_writes == 0) {
416 m_controller->reset_atomics();
417 m_atomic_writes = 0;
418 m_atomic_reads = 0;
420 }
421 else if (m_atomic_writes > 0) {
422 assert(m_atomic_reads > m_atomic_writes);
423 cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
424 assert(false);
425 }
426 ctype = CacheRequestType_IFETCH;
427 break;
428 case RubyRequestType_LD:
429 if (m_atomic_reads > 0 && m_atomic_writes == 0) {
430 m_controller->reset_atomics();
419 }
420 else if (m_atomic_writes > 0) {
421 assert(m_atomic_reads > m_atomic_writes);
422 cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
423 assert(false);
424 }
425 ctype = CacheRequestType_IFETCH;
426 break;
427 case RubyRequestType_LD:
428 if (m_atomic_reads > 0 && m_atomic_writes == 0) {
429 m_controller->reset_atomics();
430 m_atomic_writes = 0;
431 m_atomic_reads = 0;
431 }
432 else if (m_atomic_writes > 0) {
433 assert(m_atomic_reads > m_atomic_writes);
434 cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
435 assert(false);
436 }
437 ctype = CacheRequestType_LD;
438 break;
439 case RubyRequestType_ST:
440 if (m_atomic_reads > 0 && m_atomic_writes == 0) {
441 m_controller->reset_atomics();
432 }
433 else if (m_atomic_writes > 0) {
434 assert(m_atomic_reads > m_atomic_writes);
435 cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
436 assert(false);
437 }
438 ctype = CacheRequestType_LD;
439 break;
440 case RubyRequestType_ST:
441 if (m_atomic_reads > 0 && m_atomic_writes == 0) {
442 m_controller->reset_atomics();
443 m_atomic_writes = 0;
444 m_atomic_reads = 0;
442 }
443 else if (m_atomic_writes > 0) {
444 assert(m_atomic_reads > m_atomic_writes);
445 cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
446 assert(false);
447 }
448 ctype = CacheRequestType_ST;
449 break;

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446 else if (m_atomic_writes > 0) {
447 assert(m_atomic_reads > m_atomic_writes);
448 cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
449 assert(false);
450 }
451 ctype = CacheRequestType_ST;
452 break;

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