Sequencer.cc (11005:e7f403b6b76f) Sequencer.cc (11019:fc1e41e88fd3)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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53
54Sequencer::Sequencer(const Params *p)
55 : RubyPort(p), m_IncompleteTimes(MachineType_NUM), deadlockCheckEvent(this)
56{
57 m_outstanding_count = 0;
58
59 m_instCache_ptr = p->icache;
60 m_dataCache_ptr = p->dcache;
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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53
54Sequencer::Sequencer(const Params *p)
55 : RubyPort(p), m_IncompleteTimes(MachineType_NUM), deadlockCheckEvent(this)
56{
57 m_outstanding_count = 0;
58
59 m_instCache_ptr = p->icache;
60 m_dataCache_ptr = p->dcache;
61 m_data_cache_hit_latency = p->dcache_hit_latency;
62 m_inst_cache_hit_latency = p->icache_hit_latency;
61 m_max_outstanding_requests = p->max_outstanding_requests;
62 m_deadlock_threshold = p->deadlock_threshold;
63
64 assert(m_max_outstanding_requests > 0);
65 assert(m_deadlock_threshold > 0);
66 assert(m_instCache_ptr != NULL);
67 assert(m_dataCache_ptr != NULL);
63 m_max_outstanding_requests = p->max_outstanding_requests;
64 m_deadlock_threshold = p->deadlock_threshold;
65
66 assert(m_max_outstanding_requests > 0);
67 assert(m_deadlock_threshold > 0);
68 assert(m_instCache_ptr != NULL);
69 assert(m_dataCache_ptr != NULL);
70 assert(m_data_cache_hit_latency > 0);
71 assert(m_inst_cache_hit_latency > 0);
68
69 m_usingNetworkTester = p->using_network_tester;
70}
71
72Sequencer::~Sequencer()
73{
74}
75

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686 RubyAccessMode_Supervisor, pkt,
687 PrefetchBit_No, proc_id);
688
689 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
690 curTick(), m_version, "Seq", "Begin", "", "",
691 msg->getPhysicalAddress(),
692 RubyRequestType_to_string(secondary_type));
693
72
73 m_usingNetworkTester = p->using_network_tester;
74}
75
76Sequencer::~Sequencer()
77{
78}
79

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690 RubyAccessMode_Supervisor, pkt,
691 PrefetchBit_No, proc_id);
692
693 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
694 curTick(), m_version, "Seq", "Begin", "", "",
695 msg->getPhysicalAddress(),
696 RubyRequestType_to_string(secondary_type));
697
694 Cycles latency(0); // initialzed to an null value
695
698 // The Sequencer currently assesses instruction and data cache hit latency
699 // for the top-level caches at the beginning of a memory access.
700 // TODO: Eventually, this latency should be moved to represent the actual
701 // cache access latency portion of the memory access. This will require
702 // changing cache controller protocol files to assess the latency on the
703 // access response path.
704 Cycles latency(0); // Initialize to zero to catch misconfigured latency
696 if (secondary_type == RubyRequestType_IFETCH)
705 if (secondary_type == RubyRequestType_IFETCH)
697 latency = m_instCache_ptr->getLatency();
706 latency = m_inst_cache_hit_latency;
698 else
707 else
699 latency = m_dataCache_ptr->getLatency();
708 latency = m_data_cache_hit_latency;
700
701 // Send the message to the cache controller
702 assert(latency > 0);
703
704 assert(m_mandatory_q_ptr != NULL);
705 m_mandatory_q_ptr->enqueue(msg, latency);
706}
707

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710 // Send the message to the cache controller
711 assert(latency > 0);
712
713 assert(m_mandatory_q_ptr != NULL);
714 m_mandatory_q_ptr->enqueue(msg, latency);
715}
716

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