Sequencer.cc (10089:bc3126a05a7f) Sequencer.cc (10467:dcf27c8220ac)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/x86/ldstflags.hh"
29#include "base/misc.hh"
30#include "base/str.hh"
30#include "base/misc.hh"
31#include "base/str.hh"
31#include "config/the_isa.hh"
32#if THE_ISA == X86_ISA
33#include "arch/x86/insts/microldstop.hh"
34#endif // X86_ISA
35#include "cpu/testers/rubytest/RubyTester.hh"
36#include "debug/MemoryAccess.hh"
37#include "debug/ProtocolTrace.hh"
38#include "debug/RubySequencer.hh"
39#include "debug/RubyStats.hh"
40#include "mem/protocol/PrefetchBit.hh"
41#include "mem/protocol/RubyAccessMode.hh"
42#include "mem/ruby/common/Global.hh"
43#include "mem/ruby/profiler/Profiler.hh"
44#include "mem/ruby/slicc_interface/RubyRequest.hh"
45#include "mem/ruby/system/Sequencer.hh"
46#include "mem/ruby/system/System.hh"
47#include "mem/packet.hh"
32#include "cpu/testers/rubytest/RubyTester.hh"
33#include "debug/MemoryAccess.hh"
34#include "debug/ProtocolTrace.hh"
35#include "debug/RubySequencer.hh"
36#include "debug/RubyStats.hh"
37#include "mem/protocol/PrefetchBit.hh"
38#include "mem/protocol/RubyAccessMode.hh"
39#include "mem/ruby/common/Global.hh"
40#include "mem/ruby/profiler/Profiler.hh"
41#include "mem/ruby/slicc_interface/RubyRequest.hh"
42#include "mem/ruby/system/Sequencer.hh"
43#include "mem/ruby/system/System.hh"
44#include "mem/packet.hh"
45#include "sim/system.hh"
48
49using namespace std;
50
51Sequencer *
52RubySequencerParams::create()
53{
54 return new Sequencer(this);
55}

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625 primary_type = RubyRequestType_Locked_RMW_Read;
626 }
627 secondary_type = RubyRequestType_ST;
628 } else {
629 if (pkt->isRead()) {
630 if (pkt->req->isInstFetch()) {
631 primary_type = secondary_type = RubyRequestType_IFETCH;
632 } else {
46
47using namespace std;
48
49Sequencer *
50RubySequencerParams::create()
51{
52 return new Sequencer(this);
53}

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623 primary_type = RubyRequestType_Locked_RMW_Read;
624 }
625 secondary_type = RubyRequestType_ST;
626 } else {
627 if (pkt->isRead()) {
628 if (pkt->req->isInstFetch()) {
629 primary_type = secondary_type = RubyRequestType_IFETCH;
630 } else {
633#if THE_ISA == X86_ISA
634 uint32_t flags = pkt->req->getFlags();
635 bool storeCheck = flags &
636 (TheISA::StoreCheck << TheISA::FlagShift);
637#else
638 bool storeCheck = false;
631 bool storeCheck = false;
639#endif // X86_ISA
632 // only X86 need the store check
633 if (system->getArch() == Arch::X86ISA) {
634 uint32_t flags = pkt->req->getFlags();
635 storeCheck = flags &
636 (X86ISA::StoreCheck << X86ISA::FlagShift);
637 }
640 if (storeCheck) {
641 primary_type = RubyRequestType_RMW_Read;
642 secondary_type = RubyRequestType_ST;
643 } else {
644 primary_type = secondary_type = RubyRequestType_LD;
645 }
646 }
647 } else if (pkt->isWrite()) {

--- 182 unchanged lines hidden --- 		638 if (storeCheck) {
639 primary_type = RubyRequestType_RMW_Read;
640 secondary_type = RubyRequestType_ST;
641 } else {
642 primary_type = secondary_type = RubyRequestType_LD;
643 }
644 }
645 } else if (pkt->isWrite()) {

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