1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 41 unchanged lines hidden (view full) --- 50 51Sequencer * 52RubySequencerParams::create() 53{ 54 return new Sequencer(this); 55} 56 57Sequencer::Sequencer(const Params *p) |
58 : RubyPort(p), m_IncompleteTimes(MachineType_NUM), deadlockCheckEvent(this) |
59{ |
60 m_outstanding_count = 0; 61 62 m_instCache_ptr = p->icache; 63 m_dataCache_ptr = p->dcache; 64 m_max_outstanding_requests = p->max_outstanding_requests; 65 m_deadlock_threshold = p->deadlock_threshold; 66 67 assert(m_max_outstanding_requests > 0); --- 55 unchanged lines hidden (view full) --- 123 assert(m_outstanding_count == total_outstanding); 124 125 if (m_outstanding_count > 0) { 126 // If there are still outstanding requests, keep checking 127 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 128 } 129} 130 |
131void Sequencer::resetStats() |
132{ |
133 m_latencyHist.reset(); 134 m_hitLatencyHist.reset(); 135 m_missLatencyHist.reset(); |
136 for (int i = 0; i < RubyRequestType_NUM; i++) { |
137 m_typeLatencyHist[i]->reset(); 138 m_hitTypeLatencyHist[i]->reset(); 139 m_missTypeLatencyHist[i]->reset(); |
140 for (int j = 0; j < MachineType_NUM; j++) { |
141 m_hitTypeMachLatencyHist[i][j]->reset(); 142 m_missTypeMachLatencyHist[i][j]->reset(); |
143 } 144 } 145 |
146 for (int i = 0; i < MachineType_NUM; i++) { |
147 m_missMachLatencyHist[i]->reset(); 148 m_hitMachLatencyHist[i]->reset(); |
149 |
150 m_IssueToInitialDelayHist[i]->reset(); 151 m_InitialToForwardDelayHist[i]->reset(); 152 m_ForwardToFirstResponseDelayHist[i]->reset(); 153 m_FirstResponseToCompletionDelayHist[i]->reset(); |
154 155 m_IncompleteTimes[i] = 0; 156 } 157} 158 159void |
160Sequencer::printProgress(ostream& out) const 161{ 162#if 0 163 int total_demand = 0; 164 out << "Sequencer Stats Version " << m_version << endl; 165 out << "Current time = " << g_system_ptr->getTime() << endl; 166 out << "---------------" << endl; 167 out << "outstanding requests" << endl; --- 67 unchanged lines hidden (view full) --- 235 (request_type == RubyRequestType_Store_Conditional) || 236 (request_type == RubyRequestType_Locked_RMW_Read) || 237 (request_type == RubyRequestType_Locked_RMW_Write) || 238 (request_type == RubyRequestType_FLUSH)) { 239 240 // Check if there is any outstanding read request for the same 241 // cache line. 242 if (m_readRequestTable.count(line_addr) > 0) { |
243 m_store_waiting_on_load++; |
244 return RequestStatus_Aliased; 245 } 246 247 pair<RequestTable::iterator, bool> r = 248 m_writeRequestTable.insert(default_entry); 249 if (r.second) { 250 RequestTable::iterator i = r.first; 251 i->second = new SequencerRequest(pkt, request_type, curCycle()); 252 m_outstanding_count++; 253 } else { 254 // There is an outstanding write request for the cache line |
255 m_store_waiting_on_store++; |
256 return RequestStatus_Aliased; 257 } 258 } else { 259 // Check if there is any outstanding write request for the same 260 // cache line. 261 if (m_writeRequestTable.count(line_addr) > 0) { |
262 m_load_waiting_on_store++; |
263 return RequestStatus_Aliased; 264 } 265 266 pair<RequestTable::iterator, bool> r = 267 m_readRequestTable.insert(default_entry); 268 269 if (r.second) { 270 RequestTable::iterator i = r.first; 271 i->second = new SequencerRequest(pkt, request_type, curCycle()); 272 m_outstanding_count++; 273 } else { 274 // There is an outstanding read request for the cache line |
275 m_load_waiting_on_load++; |
276 return RequestStatus_Aliased; 277 } 278 } 279 |
280 m_outstandReqHist.sample(m_outstanding_count); |
281 assert(m_outstanding_count == 282 (m_writeRequestTable.size() + m_readRequestTable.size())); 283 284 return RequestStatus_Ready; 285} 286 287void 288Sequencer::markRemoved() --- 87 unchanged lines hidden (view full) --- 376void 377Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type, 378 const MachineType respondingMach, 379 bool isExternalHit, Cycles issuedTime, 380 Cycles initialRequestTime, 381 Cycles forwardRequestTime, 382 Cycles firstResponseTime, Cycles completionTime) 383{ |
384 m_latencyHist.sample(cycles); 385 m_typeLatencyHist[type]->sample(cycles); |
386 387 if (isExternalHit) { |
388 m_missLatencyHist.sample(cycles); 389 m_missTypeLatencyHist[type]->sample(cycles); |
390 391 if (respondingMach != MachineType_NUM) { |
392 m_missMachLatencyHist[respondingMach]->sample(cycles); 393 m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles); |
394 395 if ((issuedTime <= initialRequestTime) && 396 (initialRequestTime <= forwardRequestTime) && 397 (forwardRequestTime <= firstResponseTime) && 398 (firstResponseTime <= completionTime)) { 399 |
400 m_IssueToInitialDelayHist[respondingMach]->sample( |
401 initialRequestTime - issuedTime); |
402 m_InitialToForwardDelayHist[respondingMach]->sample( |
403 forwardRequestTime - initialRequestTime); |
404 m_ForwardToFirstResponseDelayHist[respondingMach]->sample( |
405 firstResponseTime - forwardRequestTime); |
406 m_FirstResponseToCompletionDelayHist[respondingMach]->sample( |
407 completionTime - firstResponseTime); 408 } else { 409 m_IncompleteTimes[respondingMach]++; 410 } 411 } 412 } else { |
413 m_hitLatencyHist.sample(cycles); 414 m_hitTypeLatencyHist[type]->sample(cycles); |
415 416 if (respondingMach != MachineType_NUM) { |
417 m_hitMachLatencyHist[respondingMach]->sample(cycles); 418 m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles); |
419 } 420 } 421} 422 423void 424Sequencer::writeCallback(const Address& address, DataBlock& data, 425 const bool externalHit, const MachineType mach, 426 const Cycles initialRequestTime, --- 327 unchanged lines hidden (view full) --- 754} 755 756 757void 758Sequencer::evictionCallback(const Address& address) 759{ 760 ruby_eviction_callback(address); 761} |
762 763void 764Sequencer::regStats() 765{ 766 m_store_waiting_on_load 767 .name(name() + ".store_waiting_on_load") 768 .desc("Number of times a store aliased with a pending load") 769 .flags(Stats::nozero); 770 m_store_waiting_on_store 771 .name(name() + ".store_waiting_on_store") 772 .desc("Number of times a store aliased with a pending store") 773 .flags(Stats::nozero); 774 m_load_waiting_on_load 775 .name(name() + ".load_waiting_on_load") 776 .desc("Number of times a load aliased with a pending load") 777 .flags(Stats::nozero); 778 m_load_waiting_on_store 779 .name(name() + ".load_waiting_on_store") 780 .desc("Number of times a load aliased with a pending store") 781 .flags(Stats::nozero); 782 783 // These statistical variables are not for display. 784 // The profiler will collate these across different 785 // sequencers and display those collated statistics. 786 m_outstandReqHist.init(10); 787 m_latencyHist.init(10); 788 m_hitLatencyHist.init(10); 789 m_missLatencyHist.init(10); 790 791 for (int i = 0; i < RubyRequestType_NUM; i++) { 792 m_typeLatencyHist.push_back(new Stats::Histogram()); 793 m_typeLatencyHist[i]->init(10); 794 795 m_hitTypeLatencyHist.push_back(new Stats::Histogram()); 796 m_hitTypeLatencyHist[i]->init(10); 797 798 m_missTypeLatencyHist.push_back(new Stats::Histogram()); 799 m_missTypeLatencyHist[i]->init(10); 800 } 801 802 for (int i = 0; i < MachineType_NUM; i++) { 803 m_hitMachLatencyHist.push_back(new Stats::Histogram()); 804 m_hitMachLatencyHist[i]->init(10); 805 806 m_missMachLatencyHist.push_back(new Stats::Histogram()); 807 m_missMachLatencyHist[i]->init(10); 808 809 m_IssueToInitialDelayHist.push_back(new Stats::Histogram()); 810 m_IssueToInitialDelayHist[i]->init(10); 811 812 m_InitialToForwardDelayHist.push_back(new Stats::Histogram()); 813 m_InitialToForwardDelayHist[i]->init(10); 814 815 m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram()); 816 m_ForwardToFirstResponseDelayHist[i]->init(10); 817 818 m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram()); 819 m_FirstResponseToCompletionDelayHist[i]->init(10); 820 } 821 822 for (int i = 0; i < RubyRequestType_NUM; i++) { 823 m_hitTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 824 m_missTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 825 826 for (int j = 0; j < MachineType_NUM; j++) { 827 m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 828 m_hitTypeMachLatencyHist[i][j]->init(10); 829 830 m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 831 m_missTypeMachLatencyHist[i][j]->init(10); 832 } 833 } 834} |