1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 291 unchanged lines hidden (view full) --- 300 } 301 302 markRemoved(); 303} 304 305void 306Sequencer::writeCallback(const Address& address, DataBlock& data) 307{ |
308 writeCallback(address, GenericMachineType_NULL, data); 309} 310 311void 312Sequencer::writeCallback(const Address& address, 313 GenericMachineType mach, 314 DataBlock& data) 315{ |
316 assert(address == line_address(address)); 317 assert(m_writeRequestTable.count(line_address(address))); 318 319 RequestTable::iterator i = m_writeRequestTable.find(address); 320 assert(i != m_writeRequestTable.end()); 321 SequencerRequest* request = i->second; 322 323 m_writeRequestTable.erase(i); --- 8 unchanged lines hidden (view full) --- 332 if (request->ruby_request.type == RubyRequestType_Locked_Read) { 333 m_dataCache_ptr->setLocked(address, m_version); 334 } else if (request->ruby_request.type == RubyRequestType_RMW_Read) { 335 m_controller->blockOnQueue(address, m_mandatory_q_ptr); 336 } else if (request->ruby_request.type == RubyRequestType_RMW_Write) { 337 m_controller->unblock(address); 338 } 339 |
340 hitCallback(request, mach, data); |
341} 342 343void 344Sequencer::readCallback(const Address& address, DataBlock& data) 345{ |
346 readCallback(address, GenericMachineType_NULL, data); 347} 348 349void 350Sequencer::readCallback(const Address& address, 351 GenericMachineType mach, 352 DataBlock& data) 353{ |
354 assert(address == line_address(address)); 355 assert(m_readRequestTable.count(line_address(address))); 356 357 RequestTable::iterator i = m_readRequestTable.find(address); 358 assert(i != m_readRequestTable.end()); 359 SequencerRequest* request = i->second; 360 361 m_readRequestTable.erase(i); 362 markRemoved(); 363 364 assert((request->ruby_request.type == RubyRequestType_LD) || 365 (request->ruby_request.type == RubyRequestType_RMW_Read) || 366 (request->ruby_request.type == RubyRequestType_IFETCH)); 367 |
368 hitCallback(request, mach, data); |
369} 370 371void |
372Sequencer::hitCallback(SequencerRequest* srequest, 373 GenericMachineType mach, 374 DataBlock& data) |
375{ 376 const RubyRequest & ruby_request = srequest->ruby_request; 377 Address request_address(ruby_request.paddr); 378 Address request_line_address(ruby_request.paddr); 379 request_line_address.makeLineAddress(); 380 RubyRequestType type = ruby_request.type; 381 Time issued_time = srequest->issue_time; 382 --- 6 unchanged lines hidden (view full) --- 389 m_dataCache_ptr->setMRU(request_line_address); 390 } 391 392 assert(g_eventQueue_ptr->getTime() >= issued_time); 393 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time; 394 395 // Profile the miss latency for all non-zero demand misses 396 if (miss_latency != 0) { |
397 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach); |
398 399 if (Debug::getProtocolTrace()) { 400 g_system_ptr->getProfiler()-> 401 profileTransition("Seq", m_version, 402 Address(ruby_request.paddr), "", "Done", "", 403 csprintf("%d cycles", miss_latency)); 404 } 405 } --- 254 unchanged lines hidden --- |