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< m_data_cache_hit_latency = p->dcache_hit_latency;
< m_inst_cache_hit_latency = p->icache_hit_latency;
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< assert(m_data_cache_hit_latency > 0);
< assert(m_inst_cache_hit_latency > 0);
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< // The Sequencer currently assesses instruction and data cache hit latency
< // for the top-level caches at the beginning of a memory access.
< // TODO: Eventually, this latency should be moved to represent the actual
< // cache access latency portion of the memory access. This will require
< // changing cache controller protocol files to assess the latency on the
< // access response path.
< Cycles latency(0); // Initialize to zero to catch misconfigured latency
< if (secondary_type == RubyRequestType_IFETCH)
< latency = m_inst_cache_hit_latency;
< else
< latency = m_data_cache_hit_latency;
<
< // Send the message to the cache controller
---
> Tick latency = cyclesToTicks(
> m_controller->mandatoryQueueLatency(secondary_type));
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< m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(latency));
---
> m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);