60a61,62
> m_data_cache_hit_latency = p->dcache_hit_latency;
> m_inst_cache_hit_latency = p->icache_hit_latency;
67a70,71
> assert(m_data_cache_hit_latency > 0);
> assert(m_inst_cache_hit_latency > 0);
694,695c698,704
< Cycles latency(0); // initialzed to an null value
<
---
> // The Sequencer currently assesses instruction and data cache hit latency
> // for the top-level caches at the beginning of a memory access.
> // TODO: Eventually, this latency should be moved to represent the actual
> // cache access latency portion of the memory access. This will require
> // changing cache controller protocol files to assess the latency on the
> // access response path.
> Cycles latency(0); // Initialize to zero to catch misconfigured latency
697c706
< latency = m_instCache_ptr->getLatency();
---
> latency = m_inst_cache_hit_latency;
699c708
< latency = m_dataCache_ptr->getLatency();
---
> latency = m_data_cache_hit_latency;