75
76 m_runningGarnetStandalone = p->garnet_standalone;
77}
78
79Sequencer::~Sequencer()
80{
81}
82
83void
84Sequencer::wakeup()
85{
86 assert(drainState() != DrainState::Draining);
87
88 // Check for deadlock of any of the requests
89 Cycles current_time = curCycle();
90
91 // Check across all outstanding requests
92 int total_outstanding = 0;
93
94 RequestTable::iterator read = m_readRequestTable.begin();
95 RequestTable::iterator read_end = m_readRequestTable.end();
96 for (; read != read_end; ++read) {
97 SequencerRequest* request = read->second;
98 if (current_time - request->issue_time < m_deadlock_threshold)
99 continue;
100
101 panic("Possible Deadlock detected. Aborting!\n"
102 "version: %d request.paddr: 0x%x m_readRequestTable: %d "
103 "current time: %u issue_time: %d difference: %d\n", m_version,
104 request->pkt->getAddr(), m_readRequestTable.size(),
105 current_time * clockPeriod(), request->issue_time * clockPeriod(),
106 (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
107 }
108
109 RequestTable::iterator write = m_writeRequestTable.begin();
110 RequestTable::iterator write_end = m_writeRequestTable.end();
111 for (; write != write_end; ++write) {
112 SequencerRequest* request = write->second;
113 if (current_time - request->issue_time < m_deadlock_threshold)
114 continue;
115
116 panic("Possible Deadlock detected. Aborting!\n"
117 "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
118 "current time: %u issue_time: %d difference: %d\n", m_version,
119 request->pkt->getAddr(), m_writeRequestTable.size(),
120 current_time * clockPeriod(), request->issue_time * clockPeriod(),
121 (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
122 }
123
124 total_outstanding += m_writeRequestTable.size();
125 total_outstanding += m_readRequestTable.size();
126
127 assert(m_outstanding_count == total_outstanding);
128
129 if (m_outstanding_count > 0) {
130 // If there are still outstanding requests, keep checking
131 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
132 }
133}
134
135void Sequencer::resetStats()
136{
137 m_latencyHist.reset();
138 m_hitLatencyHist.reset();
139 m_missLatencyHist.reset();
140 for (int i = 0; i < RubyRequestType_NUM; i++) {
141 m_typeLatencyHist[i]->reset();
142 m_hitTypeLatencyHist[i]->reset();
143 m_missTypeLatencyHist[i]->reset();
144 for (int j = 0; j < MachineType_NUM; j++) {
145 m_hitTypeMachLatencyHist[i][j]->reset();
146 m_missTypeMachLatencyHist[i][j]->reset();
147 }
148 }
149
150 for (int i = 0; i < MachineType_NUM; i++) {
151 m_missMachLatencyHist[i]->reset();
152 m_hitMachLatencyHist[i]->reset();
153
154 m_IssueToInitialDelayHist[i]->reset();
155 m_InitialToForwardDelayHist[i]->reset();
156 m_ForwardToFirstResponseDelayHist[i]->reset();
157 m_FirstResponseToCompletionDelayHist[i]->reset();
158
159 m_IncompleteTimes[i] = 0;
160 }
161}
162
163// Insert the request on the correct request table. Return true if
164// the entry was already present.
165RequestStatus
166Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
167{
168 assert(m_outstanding_count ==
169 (m_writeRequestTable.size() + m_readRequestTable.size()));
170
171 // See if we should schedule a deadlock check
172 if (!deadlockCheckEvent.scheduled() &&
173 drainState() != DrainState::Draining) {
174 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
175 }
176
177 Addr line_addr = makeLineAddress(pkt->getAddr());
178
179 // Check if the line is blocked for a Locked_RMW
180 if (m_controller->isBlocked(line_addr) &&
181 (request_type != RubyRequestType_Locked_RMW_Write)) {
182 // Return that this request's cache line address aliases with
183 // a prior request that locked the cache line. The request cannot
184 // proceed until the cache line is unlocked by a Locked_RMW_Write
185 return RequestStatus_Aliased;
186 }
187
188 // Create a default entry, mapping the address to NULL, the cast is
189 // there to make gcc 4.4 happy
190 RequestTable::value_type default_entry(line_addr,
191 (SequencerRequest*) NULL);
192
193 if ((request_type == RubyRequestType_ST) ||
194 (request_type == RubyRequestType_RMW_Read) ||
195 (request_type == RubyRequestType_RMW_Write) ||
196 (request_type == RubyRequestType_Load_Linked) ||
197 (request_type == RubyRequestType_Store_Conditional) ||
198 (request_type == RubyRequestType_Locked_RMW_Read) ||
199 (request_type == RubyRequestType_Locked_RMW_Write) ||
200 (request_type == RubyRequestType_FLUSH)) {
201
202 // Check if there is any outstanding read request for the same
203 // cache line.
204 if (m_readRequestTable.count(line_addr) > 0) {
205 m_store_waiting_on_load++;
206 return RequestStatus_Aliased;
207 }
208
209 pair<RequestTable::iterator, bool> r =
210 m_writeRequestTable.insert(default_entry);
211 if (r.second) {
212 RequestTable::iterator i = r.first;
213 i->second = new SequencerRequest(pkt, request_type, curCycle());
214 m_outstanding_count++;
215 } else {
216 // There is an outstanding write request for the cache line
217 m_store_waiting_on_store++;
218 return RequestStatus_Aliased;
219 }
220 } else {
221 // Check if there is any outstanding write request for the same
222 // cache line.
223 if (m_writeRequestTable.count(line_addr) > 0) {
224 m_load_waiting_on_store++;
225 return RequestStatus_Aliased;
226 }
227
228 pair<RequestTable::iterator, bool> r =
229 m_readRequestTable.insert(default_entry);
230
231 if (r.second) {
232 RequestTable::iterator i = r.first;
233 i->second = new SequencerRequest(pkt, request_type, curCycle());
234 m_outstanding_count++;
235 } else {
236 // There is an outstanding read request for the cache line
237 m_load_waiting_on_load++;
238 return RequestStatus_Aliased;
239 }
240 }
241
242 m_outstandReqHist.sample(m_outstanding_count);
243 assert(m_outstanding_count ==
244 (m_writeRequestTable.size() + m_readRequestTable.size()));
245
246 return RequestStatus_Ready;
247}
248
249void
250Sequencer::markRemoved()
251{
252 m_outstanding_count--;
253 assert(m_outstanding_count ==
254 m_writeRequestTable.size() + m_readRequestTable.size());
255}
256
257void
258Sequencer::invalidateSC(Addr address)
259{
260 AbstractCacheEntry *e = m_dataCache_ptr->lookup(address);
261 // The controller has lost the coherence permissions, hence the lock
262 // on the cache line maintained by the cache should be cleared.
263 if (e && e->isLocked(m_version)) {
264 e->clearLocked();
265 }
266}
267
268bool
269Sequencer::handleLlsc(Addr address, SequencerRequest* request)
270{
271 AbstractCacheEntry *e = m_dataCache_ptr->lookup(address);
272 if (!e)
273 return true;
274
275 // The success flag indicates whether the LLSC operation was successful.
276 // LL ops will always succeed, but SC may fail if the cache line is no
277 // longer locked.
278 bool success = true;
279 if (request->m_type == RubyRequestType_Store_Conditional) {
280 if (!e->isLocked(m_version)) {
281 //
282 // For failed SC requests, indicate the failure to the cpu by
283 // setting the extra data to zero.
284 //
285 request->pkt->req->setExtraData(0);
286 success = false;
287 } else {
288 //
289 // For successful SC requests, indicate the success to the cpu by
290 // setting the extra data to one.
291 //
292 request->pkt->req->setExtraData(1);
293 }
294 //
295 // Independent of success, all SC operations must clear the lock
296 //
297 e->clearLocked();
298 } else if (request->m_type == RubyRequestType_Load_Linked) {
299 //
300 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
301 // previously locked cache lines?
302 //
303 e->setLocked(m_version);
304 } else if (e->isLocked(m_version)) {
305 //
306 // Normal writes should clear the locked address
307 //
308 e->clearLocked();
309 }
310 return success;
311}
312
313void
314Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type,
315 const MachineType respondingMach,
316 bool isExternalHit, Cycles issuedTime,
317 Cycles initialRequestTime,
318 Cycles forwardRequestTime,
319 Cycles firstResponseTime, Cycles completionTime)
320{
321 m_latencyHist.sample(cycles);
322 m_typeLatencyHist[type]->sample(cycles);
323
324 if (isExternalHit) {
325 m_missLatencyHist.sample(cycles);
326 m_missTypeLatencyHist[type]->sample(cycles);
327
328 if (respondingMach != MachineType_NUM) {
329 m_missMachLatencyHist[respondingMach]->sample(cycles);
330 m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles);
331
332 if ((issuedTime <= initialRequestTime) &&
333 (initialRequestTime <= forwardRequestTime) &&
334 (forwardRequestTime <= firstResponseTime) &&
335 (firstResponseTime <= completionTime)) {
336
337 m_IssueToInitialDelayHist[respondingMach]->sample(
338 initialRequestTime - issuedTime);
339 m_InitialToForwardDelayHist[respondingMach]->sample(
340 forwardRequestTime - initialRequestTime);
341 m_ForwardToFirstResponseDelayHist[respondingMach]->sample(
342 firstResponseTime - forwardRequestTime);
343 m_FirstResponseToCompletionDelayHist[respondingMach]->sample(
344 completionTime - firstResponseTime);
345 } else {
346 m_IncompleteTimes[respondingMach]++;
347 }
348 }
349 } else {
350 m_hitLatencyHist.sample(cycles);
351 m_hitTypeLatencyHist[type]->sample(cycles);
352
353 if (respondingMach != MachineType_NUM) {
354 m_hitMachLatencyHist[respondingMach]->sample(cycles);
355 m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles);
356 }
357 }
358}
359
360void
361Sequencer::writeCallback(Addr address, DataBlock& data,
362 const bool externalHit, const MachineType mach,
363 const Cycles initialRequestTime,
364 const Cycles forwardRequestTime,
365 const Cycles firstResponseTime)
366{
367 assert(address == makeLineAddress(address));
368 assert(m_writeRequestTable.count(makeLineAddress(address)));
369
370 RequestTable::iterator i = m_writeRequestTable.find(address);
371 assert(i != m_writeRequestTable.end());
372 SequencerRequest* request = i->second;
373
374 m_writeRequestTable.erase(i);
375 markRemoved();
376
377 assert((request->m_type == RubyRequestType_ST) ||
378 (request->m_type == RubyRequestType_ATOMIC) ||
379 (request->m_type == RubyRequestType_RMW_Read) ||
380 (request->m_type == RubyRequestType_RMW_Write) ||
381 (request->m_type == RubyRequestType_Load_Linked) ||
382 (request->m_type == RubyRequestType_Store_Conditional) ||
383 (request->m_type == RubyRequestType_Locked_RMW_Read) ||
384 (request->m_type == RubyRequestType_Locked_RMW_Write) ||
385 (request->m_type == RubyRequestType_FLUSH));
386
387 //
388 // For Alpha, properly handle LL, SC, and write requests with respect to
389 // locked cache blocks.
390 //
391 // Not valid for Garnet_standalone protocl
392 //
393 bool success = true;
394 if (!m_runningGarnetStandalone)
395 success = handleLlsc(address, request);
396
397 // Handle SLICC block_on behavior for Locked_RMW accesses. NOTE: the
398 // address variable here is assumed to be a line address, so when
399 // blocking buffers, must check line addresses.
400 if (request->m_type == RubyRequestType_Locked_RMW_Read) {
401 // blockOnQueue blocks all first-level cache controller queues
402 // waiting on memory accesses for the specified address that go to
403 // the specified queue. In this case, a Locked_RMW_Write must go to
404 // the mandatory_q before unblocking the first-level controller.
405 // This will block standard loads, stores, ifetches, etc.
406 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
407 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
408 m_controller->unblock(address);
409 }
410
411 hitCallback(request, data, success, mach, externalHit,
412 initialRequestTime, forwardRequestTime, firstResponseTime);
413}
414
415void
416Sequencer::readCallback(Addr address, DataBlock& data,
417 bool externalHit, const MachineType mach,
418 Cycles initialRequestTime,
419 Cycles forwardRequestTime,
420 Cycles firstResponseTime)
421{
422 assert(address == makeLineAddress(address));
423 assert(m_readRequestTable.count(makeLineAddress(address)));
424
425 RequestTable::iterator i = m_readRequestTable.find(address);
426 assert(i != m_readRequestTable.end());
427 SequencerRequest* request = i->second;
428
429 m_readRequestTable.erase(i);
430 markRemoved();
431
432 assert((request->m_type == RubyRequestType_LD) ||
433 (request->m_type == RubyRequestType_IFETCH));
434
435 hitCallback(request, data, true, mach, externalHit,
436 initialRequestTime, forwardRequestTime, firstResponseTime);
437}
438
439void
440Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
441 bool llscSuccess,
442 const MachineType mach, const bool externalHit,
443 const Cycles initialRequestTime,
444 const Cycles forwardRequestTime,
445 const Cycles firstResponseTime)
446{
447 warn_once("Replacement policy updates recently became the responsibility "
448 "of SLICC state machines. Make sure to setMRU() near callbacks "
449 "in .sm files!");
450
451 PacketPtr pkt = srequest->pkt;
452 Addr request_address(pkt->getAddr());
453 RubyRequestType type = srequest->m_type;
454 Cycles issued_time = srequest->issue_time;
455
456 assert(curCycle() >= issued_time);
457 Cycles total_latency = curCycle() - issued_time;
458
459 // Profile the latency for all demand accesses.
460 recordMissLatency(total_latency, type, mach, externalHit, issued_time,
461 initialRequestTime, forwardRequestTime,
462 firstResponseTime, curCycle());
463
464 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n",
465 curTick(), m_version, "Seq",
466 llscSuccess ? "Done" : "SC_Failed", "", "",
467 printAddress(request_address), total_latency);
468
469 // update the data unless it is a non-data-carrying flush
470 if (RubySystem::getWarmupEnabled()) {
471 data.setData(pkt->getConstPtr<uint8_t>(),
472 getOffset(request_address), pkt->getSize());
473 } else if (!pkt->isFlush()) {
474 if ((type == RubyRequestType_LD) ||
475 (type == RubyRequestType_IFETCH) ||
476 (type == RubyRequestType_RMW_Read) ||
477 (type == RubyRequestType_Locked_RMW_Read) ||
478 (type == RubyRequestType_Load_Linked)) {
479 pkt->setData(
480 data.getData(getOffset(request_address), pkt->getSize()));
481 DPRINTF(RubySequencer, "read data %s\n", data);
482 } else if (pkt->req->isSwap()) {
483 std::vector<uint8_t> overwrite_val(pkt->getSize());
484 pkt->writeData(&overwrite_val[0]);
485 pkt->setData(
486 data.getData(getOffset(request_address), pkt->getSize()));
487 data.setData(&overwrite_val[0],
488 getOffset(request_address), pkt->getSize());
489 DPRINTF(RubySequencer, "swap data %s\n", data);
490 } else if (type != RubyRequestType_Store_Conditional || llscSuccess) {
491 // Types of stores set the actual data here, apart from
492 // failed Store Conditional requests
493 data.setData(pkt->getConstPtr<uint8_t>(),
494 getOffset(request_address), pkt->getSize());
495 DPRINTF(RubySequencer, "set data %s\n", data);
496 }
497 }
498
499 // If using the RubyTester, update the RubyTester sender state's
500 // subBlock with the recieved data. The tester will later access
501 // this state.
502 if (m_usingRubyTester) {
503 DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n",
504 pkt->cmdString(), pkt->getAddr());
505 RubyTester::SenderState* testerSenderState =
506 pkt->findNextSenderState<RubyTester::SenderState>();
507 assert(testerSenderState);
508 testerSenderState->subBlock.mergeFrom(data);
509 }
510
511 delete srequest;
512
513 RubySystem *rs = m_ruby_system;
514 if (RubySystem::getWarmupEnabled()) {
515 assert(pkt->req);
516 delete pkt;
517 rs->m_cache_recorder->enqueueNextFetchRequest();
518 } else if (RubySystem::getCooldownEnabled()) {
519 delete pkt;
520 rs->m_cache_recorder->enqueueNextFlushRequest();
521 } else {
522 ruby_hit_callback(pkt);
523 testDrainComplete();
524 }
525}
526
527bool
528Sequencer::empty() const
529{
530 return m_writeRequestTable.empty() && m_readRequestTable.empty();
531}
532
533RequestStatus
534Sequencer::makeRequest(PacketPtr pkt)
535{
536 if (m_outstanding_count >= m_max_outstanding_requests) {
537 return RequestStatus_BufferFull;
538 }
539
540 RubyRequestType primary_type = RubyRequestType_NULL;
541 RubyRequestType secondary_type = RubyRequestType_NULL;
542
543 if (pkt->isLLSC()) {
544 //
545 // Alpha LL/SC instructions need to be handled carefully by the cache
546 // coherence protocol to ensure they follow the proper semantics. In
547 // particular, by identifying the operations as atomic, the protocol
548 // should understand that migratory sharing optimizations should not
549 // be performed (i.e. a load between the LL and SC should not steal
550 // away exclusive permission).
551 //
552 if (pkt->isWrite()) {
553 DPRINTF(RubySequencer, "Issuing SC\n");
554 primary_type = RubyRequestType_Store_Conditional;
555 } else {
556 DPRINTF(RubySequencer, "Issuing LL\n");
557 assert(pkt->isRead());
558 primary_type = RubyRequestType_Load_Linked;
559 }
560 secondary_type = RubyRequestType_ATOMIC;
561 } else if (pkt->req->isLockedRMW()) {
562 //
563 // x86 locked instructions are translated to store cache coherence
564 // requests because these requests should always be treated as read
565 // exclusive operations and should leverage any migratory sharing
566 // optimization built into the protocol.
567 //
568 if (pkt->isWrite()) {
569 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
570 primary_type = RubyRequestType_Locked_RMW_Write;
571 } else {
572 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
573 assert(pkt->isRead());
574 primary_type = RubyRequestType_Locked_RMW_Read;
575 }
576 secondary_type = RubyRequestType_ST;
577 } else {
578 //
579 // To support SwapReq, we need to check isWrite() first: a SwapReq
580 // should always be treated like a write, but since a SwapReq implies
581 // both isWrite() and isRead() are true, check isWrite() first here.
582 //
583 if (pkt->isWrite()) {
584 //
585 // Note: M5 packets do not differentiate ST from RMW_Write
586 //
587 primary_type = secondary_type = RubyRequestType_ST;
588 } else if (pkt->isRead()) {
589 if (pkt->req->isInstFetch()) {
590 primary_type = secondary_type = RubyRequestType_IFETCH;
591 } else {
592 bool storeCheck = false;
593 // only X86 need the store check
594 if (system->getArch() == Arch::X86ISA) {
595 uint32_t flags = pkt->req->getFlags();
596 storeCheck = flags &
597 (X86ISA::StoreCheck << X86ISA::FlagShift);
598 }
599 if (storeCheck) {
600 primary_type = RubyRequestType_RMW_Read;
601 secondary_type = RubyRequestType_ST;
602 } else {
603 primary_type = secondary_type = RubyRequestType_LD;
604 }
605 }
606 } else if (pkt->isFlush()) {
607 primary_type = secondary_type = RubyRequestType_FLUSH;
608 } else {
609 panic("Unsupported ruby packet type\n");
610 }
611 }
612
613 RequestStatus status = insertRequest(pkt, primary_type);
614 if (status != RequestStatus_Ready)
615 return status;
616
617 issueRequest(pkt, secondary_type);
618
619 // TODO: issue hardware prefetches here
620 return RequestStatus_Issued;
621}
622
623void
624Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
625{
626 assert(pkt != NULL);
627 ContextID proc_id = pkt->req->hasContextId() ?
628 pkt->req->contextId() : InvalidContextID;
629
630 ContextID core_id = coreId();
631
632 // If valid, copy the pc to the ruby request
633 Addr pc = 0;
634 if (pkt->req->hasPC()) {
635 pc = pkt->req->getPC();
636 }
637
638 // check if the packet has data as for example prefetch and flush
639 // requests do not
640 std::shared_ptr<RubyRequest> msg =
641 std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(),
642 pkt->isFlush() ?
643 nullptr : pkt->getPtr<uint8_t>(),
644 pkt->getSize(), pc, secondary_type,
645 RubyAccessMode_Supervisor, pkt,
646 PrefetchBit_No, proc_id, core_id);
647
648 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
649 curTick(), m_version, "Seq", "Begin", "", "",
650 printAddress(msg->getPhysicalAddress()),
651 RubyRequestType_to_string(secondary_type));
652
| 71
72 m_runningGarnetStandalone = p->garnet_standalone;
73}
74
75Sequencer::~Sequencer()
76{
77}
78
79void
80Sequencer::wakeup()
81{
82 assert(drainState() != DrainState::Draining);
83
84 // Check for deadlock of any of the requests
85 Cycles current_time = curCycle();
86
87 // Check across all outstanding requests
88 int total_outstanding = 0;
89
90 RequestTable::iterator read = m_readRequestTable.begin();
91 RequestTable::iterator read_end = m_readRequestTable.end();
92 for (; read != read_end; ++read) {
93 SequencerRequest* request = read->second;
94 if (current_time - request->issue_time < m_deadlock_threshold)
95 continue;
96
97 panic("Possible Deadlock detected. Aborting!\n"
98 "version: %d request.paddr: 0x%x m_readRequestTable: %d "
99 "current time: %u issue_time: %d difference: %d\n", m_version,
100 request->pkt->getAddr(), m_readRequestTable.size(),
101 current_time * clockPeriod(), request->issue_time * clockPeriod(),
102 (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
103 }
104
105 RequestTable::iterator write = m_writeRequestTable.begin();
106 RequestTable::iterator write_end = m_writeRequestTable.end();
107 for (; write != write_end; ++write) {
108 SequencerRequest* request = write->second;
109 if (current_time - request->issue_time < m_deadlock_threshold)
110 continue;
111
112 panic("Possible Deadlock detected. Aborting!\n"
113 "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
114 "current time: %u issue_time: %d difference: %d\n", m_version,
115 request->pkt->getAddr(), m_writeRequestTable.size(),
116 current_time * clockPeriod(), request->issue_time * clockPeriod(),
117 (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
118 }
119
120 total_outstanding += m_writeRequestTable.size();
121 total_outstanding += m_readRequestTable.size();
122
123 assert(m_outstanding_count == total_outstanding);
124
125 if (m_outstanding_count > 0) {
126 // If there are still outstanding requests, keep checking
127 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
128 }
129}
130
131void Sequencer::resetStats()
132{
133 m_latencyHist.reset();
134 m_hitLatencyHist.reset();
135 m_missLatencyHist.reset();
136 for (int i = 0; i < RubyRequestType_NUM; i++) {
137 m_typeLatencyHist[i]->reset();
138 m_hitTypeLatencyHist[i]->reset();
139 m_missTypeLatencyHist[i]->reset();
140 for (int j = 0; j < MachineType_NUM; j++) {
141 m_hitTypeMachLatencyHist[i][j]->reset();
142 m_missTypeMachLatencyHist[i][j]->reset();
143 }
144 }
145
146 for (int i = 0; i < MachineType_NUM; i++) {
147 m_missMachLatencyHist[i]->reset();
148 m_hitMachLatencyHist[i]->reset();
149
150 m_IssueToInitialDelayHist[i]->reset();
151 m_InitialToForwardDelayHist[i]->reset();
152 m_ForwardToFirstResponseDelayHist[i]->reset();
153 m_FirstResponseToCompletionDelayHist[i]->reset();
154
155 m_IncompleteTimes[i] = 0;
156 }
157}
158
159// Insert the request on the correct request table. Return true if
160// the entry was already present.
161RequestStatus
162Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
163{
164 assert(m_outstanding_count ==
165 (m_writeRequestTable.size() + m_readRequestTable.size()));
166
167 // See if we should schedule a deadlock check
168 if (!deadlockCheckEvent.scheduled() &&
169 drainState() != DrainState::Draining) {
170 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
171 }
172
173 Addr line_addr = makeLineAddress(pkt->getAddr());
174
175 // Check if the line is blocked for a Locked_RMW
176 if (m_controller->isBlocked(line_addr) &&
177 (request_type != RubyRequestType_Locked_RMW_Write)) {
178 // Return that this request's cache line address aliases with
179 // a prior request that locked the cache line. The request cannot
180 // proceed until the cache line is unlocked by a Locked_RMW_Write
181 return RequestStatus_Aliased;
182 }
183
184 // Create a default entry, mapping the address to NULL, the cast is
185 // there to make gcc 4.4 happy
186 RequestTable::value_type default_entry(line_addr,
187 (SequencerRequest*) NULL);
188
189 if ((request_type == RubyRequestType_ST) ||
190 (request_type == RubyRequestType_RMW_Read) ||
191 (request_type == RubyRequestType_RMW_Write) ||
192 (request_type == RubyRequestType_Load_Linked) ||
193 (request_type == RubyRequestType_Store_Conditional) ||
194 (request_type == RubyRequestType_Locked_RMW_Read) ||
195 (request_type == RubyRequestType_Locked_RMW_Write) ||
196 (request_type == RubyRequestType_FLUSH)) {
197
198 // Check if there is any outstanding read request for the same
199 // cache line.
200 if (m_readRequestTable.count(line_addr) > 0) {
201 m_store_waiting_on_load++;
202 return RequestStatus_Aliased;
203 }
204
205 pair<RequestTable::iterator, bool> r =
206 m_writeRequestTable.insert(default_entry);
207 if (r.second) {
208 RequestTable::iterator i = r.first;
209 i->second = new SequencerRequest(pkt, request_type, curCycle());
210 m_outstanding_count++;
211 } else {
212 // There is an outstanding write request for the cache line
213 m_store_waiting_on_store++;
214 return RequestStatus_Aliased;
215 }
216 } else {
217 // Check if there is any outstanding write request for the same
218 // cache line.
219 if (m_writeRequestTable.count(line_addr) > 0) {
220 m_load_waiting_on_store++;
221 return RequestStatus_Aliased;
222 }
223
224 pair<RequestTable::iterator, bool> r =
225 m_readRequestTable.insert(default_entry);
226
227 if (r.second) {
228 RequestTable::iterator i = r.first;
229 i->second = new SequencerRequest(pkt, request_type, curCycle());
230 m_outstanding_count++;
231 } else {
232 // There is an outstanding read request for the cache line
233 m_load_waiting_on_load++;
234 return RequestStatus_Aliased;
235 }
236 }
237
238 m_outstandReqHist.sample(m_outstanding_count);
239 assert(m_outstanding_count ==
240 (m_writeRequestTable.size() + m_readRequestTable.size()));
241
242 return RequestStatus_Ready;
243}
244
245void
246Sequencer::markRemoved()
247{
248 m_outstanding_count--;
249 assert(m_outstanding_count ==
250 m_writeRequestTable.size() + m_readRequestTable.size());
251}
252
253void
254Sequencer::invalidateSC(Addr address)
255{
256 AbstractCacheEntry *e = m_dataCache_ptr->lookup(address);
257 // The controller has lost the coherence permissions, hence the lock
258 // on the cache line maintained by the cache should be cleared.
259 if (e && e->isLocked(m_version)) {
260 e->clearLocked();
261 }
262}
263
264bool
265Sequencer::handleLlsc(Addr address, SequencerRequest* request)
266{
267 AbstractCacheEntry *e = m_dataCache_ptr->lookup(address);
268 if (!e)
269 return true;
270
271 // The success flag indicates whether the LLSC operation was successful.
272 // LL ops will always succeed, but SC may fail if the cache line is no
273 // longer locked.
274 bool success = true;
275 if (request->m_type == RubyRequestType_Store_Conditional) {
276 if (!e->isLocked(m_version)) {
277 //
278 // For failed SC requests, indicate the failure to the cpu by
279 // setting the extra data to zero.
280 //
281 request->pkt->req->setExtraData(0);
282 success = false;
283 } else {
284 //
285 // For successful SC requests, indicate the success to the cpu by
286 // setting the extra data to one.
287 //
288 request->pkt->req->setExtraData(1);
289 }
290 //
291 // Independent of success, all SC operations must clear the lock
292 //
293 e->clearLocked();
294 } else if (request->m_type == RubyRequestType_Load_Linked) {
295 //
296 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
297 // previously locked cache lines?
298 //
299 e->setLocked(m_version);
300 } else if (e->isLocked(m_version)) {
301 //
302 // Normal writes should clear the locked address
303 //
304 e->clearLocked();
305 }
306 return success;
307}
308
309void
310Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type,
311 const MachineType respondingMach,
312 bool isExternalHit, Cycles issuedTime,
313 Cycles initialRequestTime,
314 Cycles forwardRequestTime,
315 Cycles firstResponseTime, Cycles completionTime)
316{
317 m_latencyHist.sample(cycles);
318 m_typeLatencyHist[type]->sample(cycles);
319
320 if (isExternalHit) {
321 m_missLatencyHist.sample(cycles);
322 m_missTypeLatencyHist[type]->sample(cycles);
323
324 if (respondingMach != MachineType_NUM) {
325 m_missMachLatencyHist[respondingMach]->sample(cycles);
326 m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles);
327
328 if ((issuedTime <= initialRequestTime) &&
329 (initialRequestTime <= forwardRequestTime) &&
330 (forwardRequestTime <= firstResponseTime) &&
331 (firstResponseTime <= completionTime)) {
332
333 m_IssueToInitialDelayHist[respondingMach]->sample(
334 initialRequestTime - issuedTime);
335 m_InitialToForwardDelayHist[respondingMach]->sample(
336 forwardRequestTime - initialRequestTime);
337 m_ForwardToFirstResponseDelayHist[respondingMach]->sample(
338 firstResponseTime - forwardRequestTime);
339 m_FirstResponseToCompletionDelayHist[respondingMach]->sample(
340 completionTime - firstResponseTime);
341 } else {
342 m_IncompleteTimes[respondingMach]++;
343 }
344 }
345 } else {
346 m_hitLatencyHist.sample(cycles);
347 m_hitTypeLatencyHist[type]->sample(cycles);
348
349 if (respondingMach != MachineType_NUM) {
350 m_hitMachLatencyHist[respondingMach]->sample(cycles);
351 m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles);
352 }
353 }
354}
355
356void
357Sequencer::writeCallback(Addr address, DataBlock& data,
358 const bool externalHit, const MachineType mach,
359 const Cycles initialRequestTime,
360 const Cycles forwardRequestTime,
361 const Cycles firstResponseTime)
362{
363 assert(address == makeLineAddress(address));
364 assert(m_writeRequestTable.count(makeLineAddress(address)));
365
366 RequestTable::iterator i = m_writeRequestTable.find(address);
367 assert(i != m_writeRequestTable.end());
368 SequencerRequest* request = i->second;
369
370 m_writeRequestTable.erase(i);
371 markRemoved();
372
373 assert((request->m_type == RubyRequestType_ST) ||
374 (request->m_type == RubyRequestType_ATOMIC) ||
375 (request->m_type == RubyRequestType_RMW_Read) ||
376 (request->m_type == RubyRequestType_RMW_Write) ||
377 (request->m_type == RubyRequestType_Load_Linked) ||
378 (request->m_type == RubyRequestType_Store_Conditional) ||
379 (request->m_type == RubyRequestType_Locked_RMW_Read) ||
380 (request->m_type == RubyRequestType_Locked_RMW_Write) ||
381 (request->m_type == RubyRequestType_FLUSH));
382
383 //
384 // For Alpha, properly handle LL, SC, and write requests with respect to
385 // locked cache blocks.
386 //
387 // Not valid for Garnet_standalone protocl
388 //
389 bool success = true;
390 if (!m_runningGarnetStandalone)
391 success = handleLlsc(address, request);
392
393 // Handle SLICC block_on behavior for Locked_RMW accesses. NOTE: the
394 // address variable here is assumed to be a line address, so when
395 // blocking buffers, must check line addresses.
396 if (request->m_type == RubyRequestType_Locked_RMW_Read) {
397 // blockOnQueue blocks all first-level cache controller queues
398 // waiting on memory accesses for the specified address that go to
399 // the specified queue. In this case, a Locked_RMW_Write must go to
400 // the mandatory_q before unblocking the first-level controller.
401 // This will block standard loads, stores, ifetches, etc.
402 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
403 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
404 m_controller->unblock(address);
405 }
406
407 hitCallback(request, data, success, mach, externalHit,
408 initialRequestTime, forwardRequestTime, firstResponseTime);
409}
410
411void
412Sequencer::readCallback(Addr address, DataBlock& data,
413 bool externalHit, const MachineType mach,
414 Cycles initialRequestTime,
415 Cycles forwardRequestTime,
416 Cycles firstResponseTime)
417{
418 assert(address == makeLineAddress(address));
419 assert(m_readRequestTable.count(makeLineAddress(address)));
420
421 RequestTable::iterator i = m_readRequestTable.find(address);
422 assert(i != m_readRequestTable.end());
423 SequencerRequest* request = i->second;
424
425 m_readRequestTable.erase(i);
426 markRemoved();
427
428 assert((request->m_type == RubyRequestType_LD) ||
429 (request->m_type == RubyRequestType_IFETCH));
430
431 hitCallback(request, data, true, mach, externalHit,
432 initialRequestTime, forwardRequestTime, firstResponseTime);
433}
434
435void
436Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
437 bool llscSuccess,
438 const MachineType mach, const bool externalHit,
439 const Cycles initialRequestTime,
440 const Cycles forwardRequestTime,
441 const Cycles firstResponseTime)
442{
443 warn_once("Replacement policy updates recently became the responsibility "
444 "of SLICC state machines. Make sure to setMRU() near callbacks "
445 "in .sm files!");
446
447 PacketPtr pkt = srequest->pkt;
448 Addr request_address(pkt->getAddr());
449 RubyRequestType type = srequest->m_type;
450 Cycles issued_time = srequest->issue_time;
451
452 assert(curCycle() >= issued_time);
453 Cycles total_latency = curCycle() - issued_time;
454
455 // Profile the latency for all demand accesses.
456 recordMissLatency(total_latency, type, mach, externalHit, issued_time,
457 initialRequestTime, forwardRequestTime,
458 firstResponseTime, curCycle());
459
460 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n",
461 curTick(), m_version, "Seq",
462 llscSuccess ? "Done" : "SC_Failed", "", "",
463 printAddress(request_address), total_latency);
464
465 // update the data unless it is a non-data-carrying flush
466 if (RubySystem::getWarmupEnabled()) {
467 data.setData(pkt->getConstPtr<uint8_t>(),
468 getOffset(request_address), pkt->getSize());
469 } else if (!pkt->isFlush()) {
470 if ((type == RubyRequestType_LD) ||
471 (type == RubyRequestType_IFETCH) ||
472 (type == RubyRequestType_RMW_Read) ||
473 (type == RubyRequestType_Locked_RMW_Read) ||
474 (type == RubyRequestType_Load_Linked)) {
475 pkt->setData(
476 data.getData(getOffset(request_address), pkt->getSize()));
477 DPRINTF(RubySequencer, "read data %s\n", data);
478 } else if (pkt->req->isSwap()) {
479 std::vector<uint8_t> overwrite_val(pkt->getSize());
480 pkt->writeData(&overwrite_val[0]);
481 pkt->setData(
482 data.getData(getOffset(request_address), pkt->getSize()));
483 data.setData(&overwrite_val[0],
484 getOffset(request_address), pkt->getSize());
485 DPRINTF(RubySequencer, "swap data %s\n", data);
486 } else if (type != RubyRequestType_Store_Conditional || llscSuccess) {
487 // Types of stores set the actual data here, apart from
488 // failed Store Conditional requests
489 data.setData(pkt->getConstPtr<uint8_t>(),
490 getOffset(request_address), pkt->getSize());
491 DPRINTF(RubySequencer, "set data %s\n", data);
492 }
493 }
494
495 // If using the RubyTester, update the RubyTester sender state's
496 // subBlock with the recieved data. The tester will later access
497 // this state.
498 if (m_usingRubyTester) {
499 DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n",
500 pkt->cmdString(), pkt->getAddr());
501 RubyTester::SenderState* testerSenderState =
502 pkt->findNextSenderState<RubyTester::SenderState>();
503 assert(testerSenderState);
504 testerSenderState->subBlock.mergeFrom(data);
505 }
506
507 delete srequest;
508
509 RubySystem *rs = m_ruby_system;
510 if (RubySystem::getWarmupEnabled()) {
511 assert(pkt->req);
512 delete pkt;
513 rs->m_cache_recorder->enqueueNextFetchRequest();
514 } else if (RubySystem::getCooldownEnabled()) {
515 delete pkt;
516 rs->m_cache_recorder->enqueueNextFlushRequest();
517 } else {
518 ruby_hit_callback(pkt);
519 testDrainComplete();
520 }
521}
522
523bool
524Sequencer::empty() const
525{
526 return m_writeRequestTable.empty() && m_readRequestTable.empty();
527}
528
529RequestStatus
530Sequencer::makeRequest(PacketPtr pkt)
531{
532 if (m_outstanding_count >= m_max_outstanding_requests) {
533 return RequestStatus_BufferFull;
534 }
535
536 RubyRequestType primary_type = RubyRequestType_NULL;
537 RubyRequestType secondary_type = RubyRequestType_NULL;
538
539 if (pkt->isLLSC()) {
540 //
541 // Alpha LL/SC instructions need to be handled carefully by the cache
542 // coherence protocol to ensure they follow the proper semantics. In
543 // particular, by identifying the operations as atomic, the protocol
544 // should understand that migratory sharing optimizations should not
545 // be performed (i.e. a load between the LL and SC should not steal
546 // away exclusive permission).
547 //
548 if (pkt->isWrite()) {
549 DPRINTF(RubySequencer, "Issuing SC\n");
550 primary_type = RubyRequestType_Store_Conditional;
551 } else {
552 DPRINTF(RubySequencer, "Issuing LL\n");
553 assert(pkt->isRead());
554 primary_type = RubyRequestType_Load_Linked;
555 }
556 secondary_type = RubyRequestType_ATOMIC;
557 } else if (pkt->req->isLockedRMW()) {
558 //
559 // x86 locked instructions are translated to store cache coherence
560 // requests because these requests should always be treated as read
561 // exclusive operations and should leverage any migratory sharing
562 // optimization built into the protocol.
563 //
564 if (pkt->isWrite()) {
565 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
566 primary_type = RubyRequestType_Locked_RMW_Write;
567 } else {
568 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
569 assert(pkt->isRead());
570 primary_type = RubyRequestType_Locked_RMW_Read;
571 }
572 secondary_type = RubyRequestType_ST;
573 } else {
574 //
575 // To support SwapReq, we need to check isWrite() first: a SwapReq
576 // should always be treated like a write, but since a SwapReq implies
577 // both isWrite() and isRead() are true, check isWrite() first here.
578 //
579 if (pkt->isWrite()) {
580 //
581 // Note: M5 packets do not differentiate ST from RMW_Write
582 //
583 primary_type = secondary_type = RubyRequestType_ST;
584 } else if (pkt->isRead()) {
585 if (pkt->req->isInstFetch()) {
586 primary_type = secondary_type = RubyRequestType_IFETCH;
587 } else {
588 bool storeCheck = false;
589 // only X86 need the store check
590 if (system->getArch() == Arch::X86ISA) {
591 uint32_t flags = pkt->req->getFlags();
592 storeCheck = flags &
593 (X86ISA::StoreCheck << X86ISA::FlagShift);
594 }
595 if (storeCheck) {
596 primary_type = RubyRequestType_RMW_Read;
597 secondary_type = RubyRequestType_ST;
598 } else {
599 primary_type = secondary_type = RubyRequestType_LD;
600 }
601 }
602 } else if (pkt->isFlush()) {
603 primary_type = secondary_type = RubyRequestType_FLUSH;
604 } else {
605 panic("Unsupported ruby packet type\n");
606 }
607 }
608
609 RequestStatus status = insertRequest(pkt, primary_type);
610 if (status != RequestStatus_Ready)
611 return status;
612
613 issueRequest(pkt, secondary_type);
614
615 // TODO: issue hardware prefetches here
616 return RequestStatus_Issued;
617}
618
619void
620Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
621{
622 assert(pkt != NULL);
623 ContextID proc_id = pkt->req->hasContextId() ?
624 pkt->req->contextId() : InvalidContextID;
625
626 ContextID core_id = coreId();
627
628 // If valid, copy the pc to the ruby request
629 Addr pc = 0;
630 if (pkt->req->hasPC()) {
631 pc = pkt->req->getPC();
632 }
633
634 // check if the packet has data as for example prefetch and flush
635 // requests do not
636 std::shared_ptr<RubyRequest> msg =
637 std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(),
638 pkt->isFlush() ?
639 nullptr : pkt->getPtr<uint8_t>(),
640 pkt->getSize(), pc, secondary_type,
641 RubyAccessMode_Supervisor, pkt,
642 PrefetchBit_No, proc_id, core_id);
643
644 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
645 curTick(), m_version, "Seq", "Begin", "", "",
646 printAddress(msg->getPhysicalAddress()),
647 RubyRequestType_to_string(secondary_type));
648
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