68
69 m_usingNetworkTester = p->using_network_tester;
70}
71
72Sequencer::~Sequencer()
73{
74}
75
76void
77Sequencer::wakeup()
78{
79 assert(drainState() != DrainState::Draining);
80
81 // Check for deadlock of any of the requests
82 Cycles current_time = curCycle();
83
84 // Check across all outstanding requests
85 int total_outstanding = 0;
86
87 RequestTable::iterator read = m_readRequestTable.begin();
88 RequestTable::iterator read_end = m_readRequestTable.end();
89 for (; read != read_end; ++read) {
90 SequencerRequest* request = read->second;
91 if (current_time - request->issue_time < m_deadlock_threshold)
92 continue;
93
94 panic("Possible Deadlock detected. Aborting!\n"
95 "version: %d request.paddr: 0x%x m_readRequestTable: %d "
96 "current time: %u issue_time: %d difference: %d\n", m_version,
97 Address(request->pkt->getAddr()), m_readRequestTable.size(),
98 current_time * clockPeriod(), request->issue_time * clockPeriod(),
99 (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
100 }
101
102 RequestTable::iterator write = m_writeRequestTable.begin();
103 RequestTable::iterator write_end = m_writeRequestTable.end();
104 for (; write != write_end; ++write) {
105 SequencerRequest* request = write->second;
106 if (current_time - request->issue_time < m_deadlock_threshold)
107 continue;
108
109 panic("Possible Deadlock detected. Aborting!\n"
110 "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
111 "current time: %u issue_time: %d difference: %d\n", m_version,
112 Address(request->pkt->getAddr()), m_writeRequestTable.size(),
113 current_time * clockPeriod(), request->issue_time * clockPeriod(),
114 (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
115 }
116
117 total_outstanding += m_writeRequestTable.size();
118 total_outstanding += m_readRequestTable.size();
119
120 assert(m_outstanding_count == total_outstanding);
121
122 if (m_outstanding_count > 0) {
123 // If there are still outstanding requests, keep checking
124 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
125 }
126}
127
128void Sequencer::resetStats()
129{
130 m_latencyHist.reset();
131 m_hitLatencyHist.reset();
132 m_missLatencyHist.reset();
133 for (int i = 0; i < RubyRequestType_NUM; i++) {
134 m_typeLatencyHist[i]->reset();
135 m_hitTypeLatencyHist[i]->reset();
136 m_missTypeLatencyHist[i]->reset();
137 for (int j = 0; j < MachineType_NUM; j++) {
138 m_hitTypeMachLatencyHist[i][j]->reset();
139 m_missTypeMachLatencyHist[i][j]->reset();
140 }
141 }
142
143 for (int i = 0; i < MachineType_NUM; i++) {
144 m_missMachLatencyHist[i]->reset();
145 m_hitMachLatencyHist[i]->reset();
146
147 m_IssueToInitialDelayHist[i]->reset();
148 m_InitialToForwardDelayHist[i]->reset();
149 m_ForwardToFirstResponseDelayHist[i]->reset();
150 m_FirstResponseToCompletionDelayHist[i]->reset();
151
152 m_IncompleteTimes[i] = 0;
153 }
154}
155
156void
157Sequencer::printProgress(ostream& out) const
158{
159#if 0
160 int total_demand = 0;
161 out << "Sequencer Stats Version " << m_version << endl;
162 out << "Current time = " << m_ruby_system->getTime() << endl;
163 out << "---------------" << endl;
164 out << "outstanding requests" << endl;
165
166 out << "proc " << m_Read
167 << " version Requests = " << m_readRequestTable.size() << endl;
168
169 // print the request table
170 RequestTable::iterator read = m_readRequestTable.begin();
171 RequestTable::iterator read_end = m_readRequestTable.end();
172 for (; read != read_end; ++read) {
173 SequencerRequest* request = read->second;
174 out << "\tRequest[ " << i << " ] = " << request->type
175 << " Address " << rkeys[i]
176 << " Posted " << request->issue_time
177 << " PF " << PrefetchBit_No << endl;
178 total_demand++;
179 }
180
181 out << "proc " << m_version
182 << " Write Requests = " << m_writeRequestTable.size << endl;
183
184 // print the request table
185 RequestTable::iterator write = m_writeRequestTable.begin();
186 RequestTable::iterator write_end = m_writeRequestTable.end();
187 for (; write != write_end; ++write) {
188 SequencerRequest* request = write->second;
189 out << "\tRequest[ " << i << " ] = " << request.getType()
190 << " Address " << wkeys[i]
191 << " Posted " << request.getTime()
192 << " PF " << request.getPrefetch() << endl;
193 if (request.getPrefetch() == PrefetchBit_No) {
194 total_demand++;
195 }
196 }
197
198 out << endl;
199
200 out << "Total Number Outstanding: " << m_outstanding_count << endl
201 << "Total Number Demand : " << total_demand << endl
202 << "Total Number Prefetches : " << m_outstanding_count - total_demand
203 << endl << endl << endl;
204#endif
205}
206
207// Insert the request on the correct request table. Return true if
208// the entry was already present.
209RequestStatus
210Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
211{
212 assert(m_outstanding_count ==
213 (m_writeRequestTable.size() + m_readRequestTable.size()));
214
215 // See if we should schedule a deadlock check
216 if (!deadlockCheckEvent.scheduled() &&
217 drainState() != DrainState::Draining) {
218 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
219 }
220
221 Address line_addr(pkt->getAddr());
222 line_addr.makeLineAddress();
223 // Create a default entry, mapping the address to NULL, the cast is
224 // there to make gcc 4.4 happy
225 RequestTable::value_type default_entry(line_addr,
226 (SequencerRequest*) NULL);
227
228 if ((request_type == RubyRequestType_ST) ||
229 (request_type == RubyRequestType_RMW_Read) ||
230 (request_type == RubyRequestType_RMW_Write) ||
231 (request_type == RubyRequestType_Load_Linked) ||
232 (request_type == RubyRequestType_Store_Conditional) ||
233 (request_type == RubyRequestType_Locked_RMW_Read) ||
234 (request_type == RubyRequestType_Locked_RMW_Write) ||
235 (request_type == RubyRequestType_FLUSH)) {
236
237 // Check if there is any outstanding read request for the same
238 // cache line.
239 if (m_readRequestTable.count(line_addr) > 0) {
240 m_store_waiting_on_load++;
241 return RequestStatus_Aliased;
242 }
243
244 pair<RequestTable::iterator, bool> r =
245 m_writeRequestTable.insert(default_entry);
246 if (r.second) {
247 RequestTable::iterator i = r.first;
248 i->second = new SequencerRequest(pkt, request_type, curCycle());
249 m_outstanding_count++;
250 } else {
251 // There is an outstanding write request for the cache line
252 m_store_waiting_on_store++;
253 return RequestStatus_Aliased;
254 }
255 } else {
256 // Check if there is any outstanding write request for the same
257 // cache line.
258 if (m_writeRequestTable.count(line_addr) > 0) {
259 m_load_waiting_on_store++;
260 return RequestStatus_Aliased;
261 }
262
263 pair<RequestTable::iterator, bool> r =
264 m_readRequestTable.insert(default_entry);
265
266 if (r.second) {
267 RequestTable::iterator i = r.first;
268 i->second = new SequencerRequest(pkt, request_type, curCycle());
269 m_outstanding_count++;
270 } else {
271 // There is an outstanding read request for the cache line
272 m_load_waiting_on_load++;
273 return RequestStatus_Aliased;
274 }
275 }
276
277 m_outstandReqHist.sample(m_outstanding_count);
278 assert(m_outstanding_count ==
279 (m_writeRequestTable.size() + m_readRequestTable.size()));
280
281 return RequestStatus_Ready;
282}
283
284void
285Sequencer::markRemoved()
286{
287 m_outstanding_count--;
288 assert(m_outstanding_count ==
289 m_writeRequestTable.size() + m_readRequestTable.size());
290}
291
292void
293Sequencer::removeRequest(SequencerRequest* srequest)
294{
295 assert(m_outstanding_count ==
296 m_writeRequestTable.size() + m_readRequestTable.size());
297
298 Address line_addr(srequest->pkt->getAddr());
299 line_addr.makeLineAddress();
300 if ((srequest->m_type == RubyRequestType_ST) ||
301 (srequest->m_type == RubyRequestType_RMW_Read) ||
302 (srequest->m_type == RubyRequestType_RMW_Write) ||
303 (srequest->m_type == RubyRequestType_Load_Linked) ||
304 (srequest->m_type == RubyRequestType_Store_Conditional) ||
305 (srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
306 (srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
307 m_writeRequestTable.erase(line_addr);
308 } else {
309 m_readRequestTable.erase(line_addr);
310 }
311
312 markRemoved();
313}
314
315void
316Sequencer::invalidateSC(const Address& address)
317{
318 RequestTable::iterator i = m_writeRequestTable.find(address);
319 if (i != m_writeRequestTable.end()) {
320 SequencerRequest* request = i->second;
321 // The controller has lost the coherence permissions, hence the lock
322 // on the cache line maintained by the cache should be cleared.
323 if (request->m_type == RubyRequestType_Store_Conditional) {
324 m_dataCache_ptr->clearLocked(address);
325 }
326 }
327}
328
329bool
330Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
331{
332 //
333 // The success flag indicates whether the LLSC operation was successful.
334 // LL ops will always succeed, but SC may fail if the cache line is no
335 // longer locked.
336 //
337 bool success = true;
338 if (request->m_type == RubyRequestType_Store_Conditional) {
339 if (!m_dataCache_ptr->isLocked(address, m_version)) {
340 //
341 // For failed SC requests, indicate the failure to the cpu by
342 // setting the extra data to zero.
343 //
344 request->pkt->req->setExtraData(0);
345 success = false;
346 } else {
347 //
348 // For successful SC requests, indicate the success to the cpu by
349 // setting the extra data to one.
350 //
351 request->pkt->req->setExtraData(1);
352 }
353 //
354 // Independent of success, all SC operations must clear the lock
355 //
356 m_dataCache_ptr->clearLocked(address);
357 } else if (request->m_type == RubyRequestType_Load_Linked) {
358 //
359 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
360 // previously locked cache lines?
361 //
362 m_dataCache_ptr->setLocked(address, m_version);
363 } else if ((m_dataCache_ptr->isTagPresent(address)) &&
364 (m_dataCache_ptr->isLocked(address, m_version))) {
365 //
366 // Normal writes should clear the locked address
367 //
368 m_dataCache_ptr->clearLocked(address);
369 }
370 return success;
371}
372
373void
374Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type,
375 const MachineType respondingMach,
376 bool isExternalHit, Cycles issuedTime,
377 Cycles initialRequestTime,
378 Cycles forwardRequestTime,
379 Cycles firstResponseTime, Cycles completionTime)
380{
381 m_latencyHist.sample(cycles);
382 m_typeLatencyHist[type]->sample(cycles);
383
384 if (isExternalHit) {
385 m_missLatencyHist.sample(cycles);
386 m_missTypeLatencyHist[type]->sample(cycles);
387
388 if (respondingMach != MachineType_NUM) {
389 m_missMachLatencyHist[respondingMach]->sample(cycles);
390 m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles);
391
392 if ((issuedTime <= initialRequestTime) &&
393 (initialRequestTime <= forwardRequestTime) &&
394 (forwardRequestTime <= firstResponseTime) &&
395 (firstResponseTime <= completionTime)) {
396
397 m_IssueToInitialDelayHist[respondingMach]->sample(
398 initialRequestTime - issuedTime);
399 m_InitialToForwardDelayHist[respondingMach]->sample(
400 forwardRequestTime - initialRequestTime);
401 m_ForwardToFirstResponseDelayHist[respondingMach]->sample(
402 firstResponseTime - forwardRequestTime);
403 m_FirstResponseToCompletionDelayHist[respondingMach]->sample(
404 completionTime - firstResponseTime);
405 } else {
406 m_IncompleteTimes[respondingMach]++;
407 }
408 }
409 } else {
410 m_hitLatencyHist.sample(cycles);
411 m_hitTypeLatencyHist[type]->sample(cycles);
412
413 if (respondingMach != MachineType_NUM) {
414 m_hitMachLatencyHist[respondingMach]->sample(cycles);
415 m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles);
416 }
417 }
418}
419
420void
421Sequencer::writeCallback(const Address& address, DataBlock& data,
422 const bool externalHit, const MachineType mach,
423 const Cycles initialRequestTime,
424 const Cycles forwardRequestTime,
425 const Cycles firstResponseTime)
426{
427 assert(address == line_address(address));
428 assert(m_writeRequestTable.count(line_address(address)));
429
430 RequestTable::iterator i = m_writeRequestTable.find(address);
431 assert(i != m_writeRequestTable.end());
432 SequencerRequest* request = i->second;
433
434 m_writeRequestTable.erase(i);
435 markRemoved();
436
437 assert((request->m_type == RubyRequestType_ST) ||
438 (request->m_type == RubyRequestType_ATOMIC) ||
439 (request->m_type == RubyRequestType_RMW_Read) ||
440 (request->m_type == RubyRequestType_RMW_Write) ||
441 (request->m_type == RubyRequestType_Load_Linked) ||
442 (request->m_type == RubyRequestType_Store_Conditional) ||
443 (request->m_type == RubyRequestType_Locked_RMW_Read) ||
444 (request->m_type == RubyRequestType_Locked_RMW_Write) ||
445 (request->m_type == RubyRequestType_FLUSH));
446
447 //
448 // For Alpha, properly handle LL, SC, and write requests with respect to
449 // locked cache blocks.
450 //
451 // Not valid for Network_test protocl
452 //
453 bool success = true;
454 if(!m_usingNetworkTester)
455 success = handleLlsc(address, request);
456
457 if (request->m_type == RubyRequestType_Locked_RMW_Read) {
458 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
459 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
460 m_controller->unblock(address);
461 }
462
463 hitCallback(request, data, success, mach, externalHit,
464 initialRequestTime, forwardRequestTime, firstResponseTime);
465}
466
467void
468Sequencer::readCallback(const Address& address, DataBlock& data,
469 bool externalHit, const MachineType mach,
470 Cycles initialRequestTime,
471 Cycles forwardRequestTime,
472 Cycles firstResponseTime)
473{
474 assert(address == line_address(address));
475 assert(m_readRequestTable.count(line_address(address)));
476
477 RequestTable::iterator i = m_readRequestTable.find(address);
478 assert(i != m_readRequestTable.end());
479 SequencerRequest* request = i->second;
480
481 m_readRequestTable.erase(i);
482 markRemoved();
483
484 assert((request->m_type == RubyRequestType_LD) ||
485 (request->m_type == RubyRequestType_IFETCH));
486
487 hitCallback(request, data, true, mach, externalHit,
488 initialRequestTime, forwardRequestTime, firstResponseTime);
489}
490
491void
492Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
493 bool llscSuccess,
494 const MachineType mach, const bool externalHit,
495 const Cycles initialRequestTime,
496 const Cycles forwardRequestTime,
497 const Cycles firstResponseTime)
498{
499 PacketPtr pkt = srequest->pkt;
500 Address request_address(pkt->getAddr());
501 Address request_line_address(pkt->getAddr());
502 request_line_address.makeLineAddress();
503 RubyRequestType type = srequest->m_type;
504 Cycles issued_time = srequest->issue_time;
505
506 // Set this cache entry to the most recently used
507 if (type == RubyRequestType_IFETCH) {
508 m_instCache_ptr->setMRU(request_line_address);
509 } else {
510 m_dataCache_ptr->setMRU(request_line_address);
511 }
512
513 assert(curCycle() >= issued_time);
514 Cycles total_latency = curCycle() - issued_time;
515
516 // Profile the latency for all demand accesses.
517 recordMissLatency(total_latency, type, mach, externalHit, issued_time,
518 initialRequestTime, forwardRequestTime,
519 firstResponseTime, curCycle());
520
521 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
522 curTick(), m_version, "Seq",
523 llscSuccess ? "Done" : "SC_Failed", "", "",
524 request_address, total_latency);
525
526 // update the data unless it is a non-data-carrying flush
527 if (RubySystem::getWarmupEnabled()) {
528 data.setData(pkt->getConstPtr<uint8_t>(),
529 request_address.getOffset(), pkt->getSize());
530 } else if (!pkt->isFlush()) {
531 if ((type == RubyRequestType_LD) ||
532 (type == RubyRequestType_IFETCH) ||
533 (type == RubyRequestType_RMW_Read) ||
534 (type == RubyRequestType_Locked_RMW_Read) ||
535 (type == RubyRequestType_Load_Linked)) {
536 memcpy(pkt->getPtr<uint8_t>(),
537 data.getData(request_address.getOffset(), pkt->getSize()),
538 pkt->getSize());
539 DPRINTF(RubySequencer, "read data %s\n", data);
540 } else {
541 data.setData(pkt->getConstPtr<uint8_t>(),
542 request_address.getOffset(), pkt->getSize());
543 DPRINTF(RubySequencer, "set data %s\n", data);
544 }
545 }
546
547 // If using the RubyTester, update the RubyTester sender state's
548 // subBlock with the recieved data. The tester will later access
549 // this state.
550 if (m_usingRubyTester) {
551 DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n",
552 pkt->cmdString(), pkt->getAddr());
553 RubyTester::SenderState* testerSenderState =
554 pkt->findNextSenderState<RubyTester::SenderState>();
555 assert(testerSenderState);
556 testerSenderState->subBlock.mergeFrom(data);
557 }
558
559 delete srequest;
560
561 RubySystem *rs = m_ruby_system;
562 if (RubySystem::getWarmupEnabled()) {
563 assert(pkt->req);
564 delete pkt->req;
565 delete pkt;
566 rs->m_cache_recorder->enqueueNextFetchRequest();
567 } else if (RubySystem::getCooldownEnabled()) {
568 delete pkt;
569 rs->m_cache_recorder->enqueueNextFlushRequest();
570 } else {
571 ruby_hit_callback(pkt);
572 }
573}
574
575bool
576Sequencer::empty() const
577{
578 return m_writeRequestTable.empty() && m_readRequestTable.empty();
579}
580
581RequestStatus
582Sequencer::makeRequest(PacketPtr pkt)
583{
584 if (m_outstanding_count >= m_max_outstanding_requests) {
585 return RequestStatus_BufferFull;
586 }
587
588 RubyRequestType primary_type = RubyRequestType_NULL;
589 RubyRequestType secondary_type = RubyRequestType_NULL;
590
591 if (pkt->isLLSC()) {
592 //
593 // Alpha LL/SC instructions need to be handled carefully by the cache
594 // coherence protocol to ensure they follow the proper semantics. In
595 // particular, by identifying the operations as atomic, the protocol
596 // should understand that migratory sharing optimizations should not
597 // be performed (i.e. a load between the LL and SC should not steal
598 // away exclusive permission).
599 //
600 if (pkt->isWrite()) {
601 DPRINTF(RubySequencer, "Issuing SC\n");
602 primary_type = RubyRequestType_Store_Conditional;
603 } else {
604 DPRINTF(RubySequencer, "Issuing LL\n");
605 assert(pkt->isRead());
606 primary_type = RubyRequestType_Load_Linked;
607 }
608 secondary_type = RubyRequestType_ATOMIC;
609 } else if (pkt->req->isLockedRMW()) {
610 //
611 // x86 locked instructions are translated to store cache coherence
612 // requests because these requests should always be treated as read
613 // exclusive operations and should leverage any migratory sharing
614 // optimization built into the protocol.
615 //
616 if (pkt->isWrite()) {
617 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
618 primary_type = RubyRequestType_Locked_RMW_Write;
619 } else {
620 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
621 assert(pkt->isRead());
622 primary_type = RubyRequestType_Locked_RMW_Read;
623 }
624 secondary_type = RubyRequestType_ST;
625 } else {
626 if (pkt->isRead()) {
627 if (pkt->req->isInstFetch()) {
628 primary_type = secondary_type = RubyRequestType_IFETCH;
629 } else {
630 bool storeCheck = false;
631 // only X86 need the store check
632 if (system->getArch() == Arch::X86ISA) {
633 uint32_t flags = pkt->req->getFlags();
634 storeCheck = flags &
635 (X86ISA::StoreCheck << X86ISA::FlagShift);
636 }
637 if (storeCheck) {
638 primary_type = RubyRequestType_RMW_Read;
639 secondary_type = RubyRequestType_ST;
640 } else {
641 primary_type = secondary_type = RubyRequestType_LD;
642 }
643 }
644 } else if (pkt->isWrite()) {
645 //
646 // Note: M5 packets do not differentiate ST from RMW_Write
647 //
648 primary_type = secondary_type = RubyRequestType_ST;
649 } else if (pkt->isFlush()) {
650 primary_type = secondary_type = RubyRequestType_FLUSH;
651 } else {
652 panic("Unsupported ruby packet type\n");
653 }
654 }
655
656 RequestStatus status = insertRequest(pkt, primary_type);
657 if (status != RequestStatus_Ready)
658 return status;
659
660 issueRequest(pkt, secondary_type);
661
662 // TODO: issue hardware prefetches here
663 return RequestStatus_Issued;
664}
665
666void
667Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
668{
669 assert(pkt != NULL);
670 ContextID proc_id = pkt->req->hasContextId() ?
671 pkt->req->contextId() : InvalidContextID;
672
673 // If valid, copy the pc to the ruby request
674 Addr pc = 0;
675 if (pkt->req->hasPC()) {
676 pc = pkt->req->getPC();
677 }
678
679 // check if the packet has data as for example prefetch and flush
680 // requests do not
681 std::shared_ptr<RubyRequest> msg =
682 std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(),
683 pkt->isFlush() ?
684 nullptr : pkt->getPtr<uint8_t>(),
685 pkt->getSize(), pc, secondary_type,
686 RubyAccessMode_Supervisor, pkt,
687 PrefetchBit_No, proc_id);
688
689 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
690 curTick(), m_version, "Seq", "Begin", "", "",
691 msg->getPhysicalAddress(),
692 RubyRequestType_to_string(secondary_type));
693
| 72
73 m_usingNetworkTester = p->using_network_tester;
74}
75
76Sequencer::~Sequencer()
77{
78}
79
80void
81Sequencer::wakeup()
82{
83 assert(drainState() != DrainState::Draining);
84
85 // Check for deadlock of any of the requests
86 Cycles current_time = curCycle();
87
88 // Check across all outstanding requests
89 int total_outstanding = 0;
90
91 RequestTable::iterator read = m_readRequestTable.begin();
92 RequestTable::iterator read_end = m_readRequestTable.end();
93 for (; read != read_end; ++read) {
94 SequencerRequest* request = read->second;
95 if (current_time - request->issue_time < m_deadlock_threshold)
96 continue;
97
98 panic("Possible Deadlock detected. Aborting!\n"
99 "version: %d request.paddr: 0x%x m_readRequestTable: %d "
100 "current time: %u issue_time: %d difference: %d\n", m_version,
101 Address(request->pkt->getAddr()), m_readRequestTable.size(),
102 current_time * clockPeriod(), request->issue_time * clockPeriod(),
103 (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
104 }
105
106 RequestTable::iterator write = m_writeRequestTable.begin();
107 RequestTable::iterator write_end = m_writeRequestTable.end();
108 for (; write != write_end; ++write) {
109 SequencerRequest* request = write->second;
110 if (current_time - request->issue_time < m_deadlock_threshold)
111 continue;
112
113 panic("Possible Deadlock detected. Aborting!\n"
114 "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
115 "current time: %u issue_time: %d difference: %d\n", m_version,
116 Address(request->pkt->getAddr()), m_writeRequestTable.size(),
117 current_time * clockPeriod(), request->issue_time * clockPeriod(),
118 (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
119 }
120
121 total_outstanding += m_writeRequestTable.size();
122 total_outstanding += m_readRequestTable.size();
123
124 assert(m_outstanding_count == total_outstanding);
125
126 if (m_outstanding_count > 0) {
127 // If there are still outstanding requests, keep checking
128 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
129 }
130}
131
132void Sequencer::resetStats()
133{
134 m_latencyHist.reset();
135 m_hitLatencyHist.reset();
136 m_missLatencyHist.reset();
137 for (int i = 0; i < RubyRequestType_NUM; i++) {
138 m_typeLatencyHist[i]->reset();
139 m_hitTypeLatencyHist[i]->reset();
140 m_missTypeLatencyHist[i]->reset();
141 for (int j = 0; j < MachineType_NUM; j++) {
142 m_hitTypeMachLatencyHist[i][j]->reset();
143 m_missTypeMachLatencyHist[i][j]->reset();
144 }
145 }
146
147 for (int i = 0; i < MachineType_NUM; i++) {
148 m_missMachLatencyHist[i]->reset();
149 m_hitMachLatencyHist[i]->reset();
150
151 m_IssueToInitialDelayHist[i]->reset();
152 m_InitialToForwardDelayHist[i]->reset();
153 m_ForwardToFirstResponseDelayHist[i]->reset();
154 m_FirstResponseToCompletionDelayHist[i]->reset();
155
156 m_IncompleteTimes[i] = 0;
157 }
158}
159
160void
161Sequencer::printProgress(ostream& out) const
162{
163#if 0
164 int total_demand = 0;
165 out << "Sequencer Stats Version " << m_version << endl;
166 out << "Current time = " << m_ruby_system->getTime() << endl;
167 out << "---------------" << endl;
168 out << "outstanding requests" << endl;
169
170 out << "proc " << m_Read
171 << " version Requests = " << m_readRequestTable.size() << endl;
172
173 // print the request table
174 RequestTable::iterator read = m_readRequestTable.begin();
175 RequestTable::iterator read_end = m_readRequestTable.end();
176 for (; read != read_end; ++read) {
177 SequencerRequest* request = read->second;
178 out << "\tRequest[ " << i << " ] = " << request->type
179 << " Address " << rkeys[i]
180 << " Posted " << request->issue_time
181 << " PF " << PrefetchBit_No << endl;
182 total_demand++;
183 }
184
185 out << "proc " << m_version
186 << " Write Requests = " << m_writeRequestTable.size << endl;
187
188 // print the request table
189 RequestTable::iterator write = m_writeRequestTable.begin();
190 RequestTable::iterator write_end = m_writeRequestTable.end();
191 for (; write != write_end; ++write) {
192 SequencerRequest* request = write->second;
193 out << "\tRequest[ " << i << " ] = " << request.getType()
194 << " Address " << wkeys[i]
195 << " Posted " << request.getTime()
196 << " PF " << request.getPrefetch() << endl;
197 if (request.getPrefetch() == PrefetchBit_No) {
198 total_demand++;
199 }
200 }
201
202 out << endl;
203
204 out << "Total Number Outstanding: " << m_outstanding_count << endl
205 << "Total Number Demand : " << total_demand << endl
206 << "Total Number Prefetches : " << m_outstanding_count - total_demand
207 << endl << endl << endl;
208#endif
209}
210
211// Insert the request on the correct request table. Return true if
212// the entry was already present.
213RequestStatus
214Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
215{
216 assert(m_outstanding_count ==
217 (m_writeRequestTable.size() + m_readRequestTable.size()));
218
219 // See if we should schedule a deadlock check
220 if (!deadlockCheckEvent.scheduled() &&
221 drainState() != DrainState::Draining) {
222 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
223 }
224
225 Address line_addr(pkt->getAddr());
226 line_addr.makeLineAddress();
227 // Create a default entry, mapping the address to NULL, the cast is
228 // there to make gcc 4.4 happy
229 RequestTable::value_type default_entry(line_addr,
230 (SequencerRequest*) NULL);
231
232 if ((request_type == RubyRequestType_ST) ||
233 (request_type == RubyRequestType_RMW_Read) ||
234 (request_type == RubyRequestType_RMW_Write) ||
235 (request_type == RubyRequestType_Load_Linked) ||
236 (request_type == RubyRequestType_Store_Conditional) ||
237 (request_type == RubyRequestType_Locked_RMW_Read) ||
238 (request_type == RubyRequestType_Locked_RMW_Write) ||
239 (request_type == RubyRequestType_FLUSH)) {
240
241 // Check if there is any outstanding read request for the same
242 // cache line.
243 if (m_readRequestTable.count(line_addr) > 0) {
244 m_store_waiting_on_load++;
245 return RequestStatus_Aliased;
246 }
247
248 pair<RequestTable::iterator, bool> r =
249 m_writeRequestTable.insert(default_entry);
250 if (r.second) {
251 RequestTable::iterator i = r.first;
252 i->second = new SequencerRequest(pkt, request_type, curCycle());
253 m_outstanding_count++;
254 } else {
255 // There is an outstanding write request for the cache line
256 m_store_waiting_on_store++;
257 return RequestStatus_Aliased;
258 }
259 } else {
260 // Check if there is any outstanding write request for the same
261 // cache line.
262 if (m_writeRequestTable.count(line_addr) > 0) {
263 m_load_waiting_on_store++;
264 return RequestStatus_Aliased;
265 }
266
267 pair<RequestTable::iterator, bool> r =
268 m_readRequestTable.insert(default_entry);
269
270 if (r.second) {
271 RequestTable::iterator i = r.first;
272 i->second = new SequencerRequest(pkt, request_type, curCycle());
273 m_outstanding_count++;
274 } else {
275 // There is an outstanding read request for the cache line
276 m_load_waiting_on_load++;
277 return RequestStatus_Aliased;
278 }
279 }
280
281 m_outstandReqHist.sample(m_outstanding_count);
282 assert(m_outstanding_count ==
283 (m_writeRequestTable.size() + m_readRequestTable.size()));
284
285 return RequestStatus_Ready;
286}
287
288void
289Sequencer::markRemoved()
290{
291 m_outstanding_count--;
292 assert(m_outstanding_count ==
293 m_writeRequestTable.size() + m_readRequestTable.size());
294}
295
296void
297Sequencer::removeRequest(SequencerRequest* srequest)
298{
299 assert(m_outstanding_count ==
300 m_writeRequestTable.size() + m_readRequestTable.size());
301
302 Address line_addr(srequest->pkt->getAddr());
303 line_addr.makeLineAddress();
304 if ((srequest->m_type == RubyRequestType_ST) ||
305 (srequest->m_type == RubyRequestType_RMW_Read) ||
306 (srequest->m_type == RubyRequestType_RMW_Write) ||
307 (srequest->m_type == RubyRequestType_Load_Linked) ||
308 (srequest->m_type == RubyRequestType_Store_Conditional) ||
309 (srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
310 (srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
311 m_writeRequestTable.erase(line_addr);
312 } else {
313 m_readRequestTable.erase(line_addr);
314 }
315
316 markRemoved();
317}
318
319void
320Sequencer::invalidateSC(const Address& address)
321{
322 RequestTable::iterator i = m_writeRequestTable.find(address);
323 if (i != m_writeRequestTable.end()) {
324 SequencerRequest* request = i->second;
325 // The controller has lost the coherence permissions, hence the lock
326 // on the cache line maintained by the cache should be cleared.
327 if (request->m_type == RubyRequestType_Store_Conditional) {
328 m_dataCache_ptr->clearLocked(address);
329 }
330 }
331}
332
333bool
334Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
335{
336 //
337 // The success flag indicates whether the LLSC operation was successful.
338 // LL ops will always succeed, but SC may fail if the cache line is no
339 // longer locked.
340 //
341 bool success = true;
342 if (request->m_type == RubyRequestType_Store_Conditional) {
343 if (!m_dataCache_ptr->isLocked(address, m_version)) {
344 //
345 // For failed SC requests, indicate the failure to the cpu by
346 // setting the extra data to zero.
347 //
348 request->pkt->req->setExtraData(0);
349 success = false;
350 } else {
351 //
352 // For successful SC requests, indicate the success to the cpu by
353 // setting the extra data to one.
354 //
355 request->pkt->req->setExtraData(1);
356 }
357 //
358 // Independent of success, all SC operations must clear the lock
359 //
360 m_dataCache_ptr->clearLocked(address);
361 } else if (request->m_type == RubyRequestType_Load_Linked) {
362 //
363 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
364 // previously locked cache lines?
365 //
366 m_dataCache_ptr->setLocked(address, m_version);
367 } else if ((m_dataCache_ptr->isTagPresent(address)) &&
368 (m_dataCache_ptr->isLocked(address, m_version))) {
369 //
370 // Normal writes should clear the locked address
371 //
372 m_dataCache_ptr->clearLocked(address);
373 }
374 return success;
375}
376
377void
378Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type,
379 const MachineType respondingMach,
380 bool isExternalHit, Cycles issuedTime,
381 Cycles initialRequestTime,
382 Cycles forwardRequestTime,
383 Cycles firstResponseTime, Cycles completionTime)
384{
385 m_latencyHist.sample(cycles);
386 m_typeLatencyHist[type]->sample(cycles);
387
388 if (isExternalHit) {
389 m_missLatencyHist.sample(cycles);
390 m_missTypeLatencyHist[type]->sample(cycles);
391
392 if (respondingMach != MachineType_NUM) {
393 m_missMachLatencyHist[respondingMach]->sample(cycles);
394 m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles);
395
396 if ((issuedTime <= initialRequestTime) &&
397 (initialRequestTime <= forwardRequestTime) &&
398 (forwardRequestTime <= firstResponseTime) &&
399 (firstResponseTime <= completionTime)) {
400
401 m_IssueToInitialDelayHist[respondingMach]->sample(
402 initialRequestTime - issuedTime);
403 m_InitialToForwardDelayHist[respondingMach]->sample(
404 forwardRequestTime - initialRequestTime);
405 m_ForwardToFirstResponseDelayHist[respondingMach]->sample(
406 firstResponseTime - forwardRequestTime);
407 m_FirstResponseToCompletionDelayHist[respondingMach]->sample(
408 completionTime - firstResponseTime);
409 } else {
410 m_IncompleteTimes[respondingMach]++;
411 }
412 }
413 } else {
414 m_hitLatencyHist.sample(cycles);
415 m_hitTypeLatencyHist[type]->sample(cycles);
416
417 if (respondingMach != MachineType_NUM) {
418 m_hitMachLatencyHist[respondingMach]->sample(cycles);
419 m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles);
420 }
421 }
422}
423
424void
425Sequencer::writeCallback(const Address& address, DataBlock& data,
426 const bool externalHit, const MachineType mach,
427 const Cycles initialRequestTime,
428 const Cycles forwardRequestTime,
429 const Cycles firstResponseTime)
430{
431 assert(address == line_address(address));
432 assert(m_writeRequestTable.count(line_address(address)));
433
434 RequestTable::iterator i = m_writeRequestTable.find(address);
435 assert(i != m_writeRequestTable.end());
436 SequencerRequest* request = i->second;
437
438 m_writeRequestTable.erase(i);
439 markRemoved();
440
441 assert((request->m_type == RubyRequestType_ST) ||
442 (request->m_type == RubyRequestType_ATOMIC) ||
443 (request->m_type == RubyRequestType_RMW_Read) ||
444 (request->m_type == RubyRequestType_RMW_Write) ||
445 (request->m_type == RubyRequestType_Load_Linked) ||
446 (request->m_type == RubyRequestType_Store_Conditional) ||
447 (request->m_type == RubyRequestType_Locked_RMW_Read) ||
448 (request->m_type == RubyRequestType_Locked_RMW_Write) ||
449 (request->m_type == RubyRequestType_FLUSH));
450
451 //
452 // For Alpha, properly handle LL, SC, and write requests with respect to
453 // locked cache blocks.
454 //
455 // Not valid for Network_test protocl
456 //
457 bool success = true;
458 if(!m_usingNetworkTester)
459 success = handleLlsc(address, request);
460
461 if (request->m_type == RubyRequestType_Locked_RMW_Read) {
462 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
463 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
464 m_controller->unblock(address);
465 }
466
467 hitCallback(request, data, success, mach, externalHit,
468 initialRequestTime, forwardRequestTime, firstResponseTime);
469}
470
471void
472Sequencer::readCallback(const Address& address, DataBlock& data,
473 bool externalHit, const MachineType mach,
474 Cycles initialRequestTime,
475 Cycles forwardRequestTime,
476 Cycles firstResponseTime)
477{
478 assert(address == line_address(address));
479 assert(m_readRequestTable.count(line_address(address)));
480
481 RequestTable::iterator i = m_readRequestTable.find(address);
482 assert(i != m_readRequestTable.end());
483 SequencerRequest* request = i->second;
484
485 m_readRequestTable.erase(i);
486 markRemoved();
487
488 assert((request->m_type == RubyRequestType_LD) ||
489 (request->m_type == RubyRequestType_IFETCH));
490
491 hitCallback(request, data, true, mach, externalHit,
492 initialRequestTime, forwardRequestTime, firstResponseTime);
493}
494
495void
496Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
497 bool llscSuccess,
498 const MachineType mach, const bool externalHit,
499 const Cycles initialRequestTime,
500 const Cycles forwardRequestTime,
501 const Cycles firstResponseTime)
502{
503 PacketPtr pkt = srequest->pkt;
504 Address request_address(pkt->getAddr());
505 Address request_line_address(pkt->getAddr());
506 request_line_address.makeLineAddress();
507 RubyRequestType type = srequest->m_type;
508 Cycles issued_time = srequest->issue_time;
509
510 // Set this cache entry to the most recently used
511 if (type == RubyRequestType_IFETCH) {
512 m_instCache_ptr->setMRU(request_line_address);
513 } else {
514 m_dataCache_ptr->setMRU(request_line_address);
515 }
516
517 assert(curCycle() >= issued_time);
518 Cycles total_latency = curCycle() - issued_time;
519
520 // Profile the latency for all demand accesses.
521 recordMissLatency(total_latency, type, mach, externalHit, issued_time,
522 initialRequestTime, forwardRequestTime,
523 firstResponseTime, curCycle());
524
525 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
526 curTick(), m_version, "Seq",
527 llscSuccess ? "Done" : "SC_Failed", "", "",
528 request_address, total_latency);
529
530 // update the data unless it is a non-data-carrying flush
531 if (RubySystem::getWarmupEnabled()) {
532 data.setData(pkt->getConstPtr<uint8_t>(),
533 request_address.getOffset(), pkt->getSize());
534 } else if (!pkt->isFlush()) {
535 if ((type == RubyRequestType_LD) ||
536 (type == RubyRequestType_IFETCH) ||
537 (type == RubyRequestType_RMW_Read) ||
538 (type == RubyRequestType_Locked_RMW_Read) ||
539 (type == RubyRequestType_Load_Linked)) {
540 memcpy(pkt->getPtr<uint8_t>(),
541 data.getData(request_address.getOffset(), pkt->getSize()),
542 pkt->getSize());
543 DPRINTF(RubySequencer, "read data %s\n", data);
544 } else {
545 data.setData(pkt->getConstPtr<uint8_t>(),
546 request_address.getOffset(), pkt->getSize());
547 DPRINTF(RubySequencer, "set data %s\n", data);
548 }
549 }
550
551 // If using the RubyTester, update the RubyTester sender state's
552 // subBlock with the recieved data. The tester will later access
553 // this state.
554 if (m_usingRubyTester) {
555 DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n",
556 pkt->cmdString(), pkt->getAddr());
557 RubyTester::SenderState* testerSenderState =
558 pkt->findNextSenderState<RubyTester::SenderState>();
559 assert(testerSenderState);
560 testerSenderState->subBlock.mergeFrom(data);
561 }
562
563 delete srequest;
564
565 RubySystem *rs = m_ruby_system;
566 if (RubySystem::getWarmupEnabled()) {
567 assert(pkt->req);
568 delete pkt->req;
569 delete pkt;
570 rs->m_cache_recorder->enqueueNextFetchRequest();
571 } else if (RubySystem::getCooldownEnabled()) {
572 delete pkt;
573 rs->m_cache_recorder->enqueueNextFlushRequest();
574 } else {
575 ruby_hit_callback(pkt);
576 }
577}
578
579bool
580Sequencer::empty() const
581{
582 return m_writeRequestTable.empty() && m_readRequestTable.empty();
583}
584
585RequestStatus
586Sequencer::makeRequest(PacketPtr pkt)
587{
588 if (m_outstanding_count >= m_max_outstanding_requests) {
589 return RequestStatus_BufferFull;
590 }
591
592 RubyRequestType primary_type = RubyRequestType_NULL;
593 RubyRequestType secondary_type = RubyRequestType_NULL;
594
595 if (pkt->isLLSC()) {
596 //
597 // Alpha LL/SC instructions need to be handled carefully by the cache
598 // coherence protocol to ensure they follow the proper semantics. In
599 // particular, by identifying the operations as atomic, the protocol
600 // should understand that migratory sharing optimizations should not
601 // be performed (i.e. a load between the LL and SC should not steal
602 // away exclusive permission).
603 //
604 if (pkt->isWrite()) {
605 DPRINTF(RubySequencer, "Issuing SC\n");
606 primary_type = RubyRequestType_Store_Conditional;
607 } else {
608 DPRINTF(RubySequencer, "Issuing LL\n");
609 assert(pkt->isRead());
610 primary_type = RubyRequestType_Load_Linked;
611 }
612 secondary_type = RubyRequestType_ATOMIC;
613 } else if (pkt->req->isLockedRMW()) {
614 //
615 // x86 locked instructions are translated to store cache coherence
616 // requests because these requests should always be treated as read
617 // exclusive operations and should leverage any migratory sharing
618 // optimization built into the protocol.
619 //
620 if (pkt->isWrite()) {
621 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
622 primary_type = RubyRequestType_Locked_RMW_Write;
623 } else {
624 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
625 assert(pkt->isRead());
626 primary_type = RubyRequestType_Locked_RMW_Read;
627 }
628 secondary_type = RubyRequestType_ST;
629 } else {
630 if (pkt->isRead()) {
631 if (pkt->req->isInstFetch()) {
632 primary_type = secondary_type = RubyRequestType_IFETCH;
633 } else {
634 bool storeCheck = false;
635 // only X86 need the store check
636 if (system->getArch() == Arch::X86ISA) {
637 uint32_t flags = pkt->req->getFlags();
638 storeCheck = flags &
639 (X86ISA::StoreCheck << X86ISA::FlagShift);
640 }
641 if (storeCheck) {
642 primary_type = RubyRequestType_RMW_Read;
643 secondary_type = RubyRequestType_ST;
644 } else {
645 primary_type = secondary_type = RubyRequestType_LD;
646 }
647 }
648 } else if (pkt->isWrite()) {
649 //
650 // Note: M5 packets do not differentiate ST from RMW_Write
651 //
652 primary_type = secondary_type = RubyRequestType_ST;
653 } else if (pkt->isFlush()) {
654 primary_type = secondary_type = RubyRequestType_FLUSH;
655 } else {
656 panic("Unsupported ruby packet type\n");
657 }
658 }
659
660 RequestStatus status = insertRequest(pkt, primary_type);
661 if (status != RequestStatus_Ready)
662 return status;
663
664 issueRequest(pkt, secondary_type);
665
666 // TODO: issue hardware prefetches here
667 return RequestStatus_Issued;
668}
669
670void
671Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
672{
673 assert(pkt != NULL);
674 ContextID proc_id = pkt->req->hasContextId() ?
675 pkt->req->contextId() : InvalidContextID;
676
677 // If valid, copy the pc to the ruby request
678 Addr pc = 0;
679 if (pkt->req->hasPC()) {
680 pc = pkt->req->getPC();
681 }
682
683 // check if the packet has data as for example prefetch and flush
684 // requests do not
685 std::shared_ptr<RubyRequest> msg =
686 std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(),
687 pkt->isFlush() ?
688 nullptr : pkt->getPtr<uint8_t>(),
689 pkt->getSize(), pc, secondary_type,
690 RubyAccessMode_Supervisor, pkt,
691 PrefetchBit_No, proc_id);
692
693 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
694 curTick(), m_version, "Seq", "Begin", "", "",
695 msg->getPhysicalAddress(),
696 RubyRequestType_to_string(secondary_type));
697
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