1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "base/misc.hh"
30#include "base/str.hh"
31#include "config/the_isa.hh"
32#if THE_ISA == X86_ISA
33#include "arch/x86/insts/microldstop.hh"
34#endif // X86_ISA
35#include "cpu/testers/rubytest/RubyTester.hh"
36#include "debug/MemoryAccess.hh"
37#include "debug/ProtocolTrace.hh"
38#include "debug/RubySequencer.hh"
39#include "debug/RubyStats.hh"
40#include "mem/protocol/PrefetchBit.hh"
41#include "mem/protocol/RubyAccessMode.hh"
42#include "mem/ruby/buffers/MessageBuffer.hh"
43#include "mem/ruby/common/Global.hh"
44#include "mem/ruby/profiler/Profiler.hh"
45#include "mem/ruby/slicc_interface/RubyRequest.hh"
46#include "mem/ruby/system/CacheMemory.hh"
47#include "mem/ruby/system/Sequencer.hh"
48#include "mem/ruby/system/System.hh"
49#include "mem/packet.hh"
50#include "params/RubySequencer.hh"
51
52using namespace std;
53
54Sequencer *
55RubySequencerParams::create()
56{
57 return new Sequencer(this);
58}
59
60Sequencer::Sequencer(const Params *p)
61 : RubyPort(p), deadlockCheckEvent(this)
62{
63 m_store_waiting_on_load_cycles = 0;
64 m_store_waiting_on_store_cycles = 0;
65 m_load_waiting_on_store_cycles = 0;
66 m_load_waiting_on_load_cycles = 0;
67
68 m_outstanding_count = 0;
69
70 m_instCache_ptr = p->icache;
71 m_dataCache_ptr = p->dcache;
72 m_max_outstanding_requests = p->max_outstanding_requests;
73 m_deadlock_threshold = p->deadlock_threshold;
74
75 assert(m_max_outstanding_requests > 0);
76 assert(m_deadlock_threshold > 0);
77 assert(m_instCache_ptr != NULL);
78 assert(m_dataCache_ptr != NULL);
79
80 m_usingNetworkTester = p->using_network_tester;
81}
82
83Sequencer::~Sequencer()
84{
85}
86
87void
88Sequencer::wakeup()
89{
90 // Check for deadlock of any of the requests
91 Time current_time = g_eventQueue_ptr->getTime();
92
93 // Check across all outstanding requests
94 int total_outstanding = 0;
95
96 RequestTable::iterator read = m_readRequestTable.begin();
97 RequestTable::iterator read_end = m_readRequestTable.end();
98 for (; read != read_end; ++read) {
99 SequencerRequest* request = read->second;
100 if (current_time - request->issue_time < m_deadlock_threshold)
101 continue;
102
103 panic("Possible Deadlock detected. Aborting!\n"
104 "version: %d request.paddr: 0x%x m_readRequestTable: %d "
105 "current time: %u issue_time: %d difference: %d\n", m_version,
106 Address(request->pkt->getAddr()), m_readRequestTable.size(),
107 current_time, request->issue_time,
108 current_time - request->issue_time);
109 }
110
111 RequestTable::iterator write = m_writeRequestTable.begin();
112 RequestTable::iterator write_end = m_writeRequestTable.end();
113 for (; write != write_end; ++write) {
114 SequencerRequest* request = write->second;
115 if (current_time - request->issue_time < m_deadlock_threshold)
116 continue;
117
118 panic("Possible Deadlock detected. Aborting!\n"
119 "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
120 "current time: %u issue_time: %d difference: %d\n", m_version,
121 Address(request->pkt->getAddr()), m_writeRequestTable.size(),
122 current_time, request->issue_time,
123 current_time - request->issue_time);
124 }
125
126 total_outstanding += m_writeRequestTable.size();
127 total_outstanding += m_readRequestTable.size();
128
129 assert(m_outstanding_count == total_outstanding);
130
131 if (m_outstanding_count > 0) {
132 // If there are still outstanding requests, keep checking
133 schedule(deadlockCheckEvent,
134 m_deadlock_threshold * g_eventQueue_ptr->getClock() +
135 curTick());
136 }
137}
138
139void
140Sequencer::printStats(ostream & out) const
141{
142 out << "Sequencer: " << m_name << endl
143 << " store_waiting_on_load_cycles: "
144 << m_store_waiting_on_load_cycles << endl
145 << " store_waiting_on_store_cycles: "
146 << m_store_waiting_on_store_cycles << endl
147 << " load_waiting_on_load_cycles: "
148 << m_load_waiting_on_load_cycles << endl
149 << " load_waiting_on_store_cycles: "
150 << m_load_waiting_on_store_cycles << endl;
151}
152
153void
154Sequencer::printProgress(ostream& out) const
155{
156#if 0
157 int total_demand = 0;
158 out << "Sequencer Stats Version " << m_version << endl;
159 out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
160 out << "---------------" << endl;
161 out << "outstanding requests" << endl;
162
163 out << "proc " << m_Read
164 << " version Requests = " << m_readRequestTable.size() << endl;
165
166 // print the request table
167 RequestTable::iterator read = m_readRequestTable.begin();
168 RequestTable::iterator read_end = m_readRequestTable.end();
169 for (; read != read_end; ++read) {
170 SequencerRequest* request = read->second;
171 out << "\tRequest[ " << i << " ] = " << request->type
172 << " Address " << rkeys[i]
173 << " Posted " << request->issue_time
174 << " PF " << PrefetchBit_No << endl;
175 total_demand++;
176 }
177
178 out << "proc " << m_version
179 << " Write Requests = " << m_writeRequestTable.size << endl;
180
181 // print the request table
182 RequestTable::iterator write = m_writeRequestTable.begin();
183 RequestTable::iterator write_end = m_writeRequestTable.end();
184 for (; write != write_end; ++write) {
185 SequencerRequest* request = write->second;
186 out << "\tRequest[ " << i << " ] = " << request.getType()
187 << " Address " << wkeys[i]
188 << " Posted " << request.getTime()
189 << " PF " << request.getPrefetch() << endl;
190 if (request.getPrefetch() == PrefetchBit_No) {
191 total_demand++;
192 }
193 }
194
195 out << endl;
196
197 out << "Total Number Outstanding: " << m_outstanding_count << endl
198 << "Total Number Demand : " << total_demand << endl
199 << "Total Number Prefetches : " << m_outstanding_count - total_demand
200 << endl << endl << endl;
201#endif
202}
203
204// Insert the request on the correct request table. Return true if
205// the entry was already present.
206RequestStatus
207Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
208{
209 assert(m_outstanding_count ==
210 (m_writeRequestTable.size() + m_readRequestTable.size()));
211
212 // See if we should schedule a deadlock check
213 if (deadlockCheckEvent.scheduled() == false) {
214 schedule(deadlockCheckEvent,
215 m_deadlock_threshold * g_eventQueue_ptr->getClock()
216 + curTick());
217 }
218
219 Address line_addr(pkt->getAddr());
220 line_addr.makeLineAddress();
221 if ((request_type == RubyRequestType_ST) ||
222 (request_type == RubyRequestType_RMW_Read) ||
223 (request_type == RubyRequestType_RMW_Write) ||
224 (request_type == RubyRequestType_Load_Linked) ||
225 (request_type == RubyRequestType_Store_Conditional) ||
226 (request_type == RubyRequestType_Locked_RMW_Read) ||
227 (request_type == RubyRequestType_Locked_RMW_Write) ||
228 (request_type == RubyRequestType_FLUSH)) {
229
230 // Check if there is any outstanding read request for the same
231 // cache line.
232 if (m_readRequestTable.count(line_addr) > 0) {
233 m_store_waiting_on_load_cycles++;
234 return RequestStatus_Aliased;
235 }
236
237 pair<RequestTable::iterator, bool> r =
238 m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0));
239 if (r.second) {
240 RequestTable::iterator i = r.first;
241 i->second = new SequencerRequest(pkt, request_type,
242 g_eventQueue_ptr->getTime());
243 m_outstanding_count++;
244 } else {
245 // There is an outstanding write request for the cache line
246 m_store_waiting_on_store_cycles++;
247 return RequestStatus_Aliased;
248 }
249 } else {
250 // Check if there is any outstanding write request for the same
251 // cache line.
252 if (m_writeRequestTable.count(line_addr) > 0) {
253 m_load_waiting_on_store_cycles++;
254 return RequestStatus_Aliased;
255 }
256
257 pair<RequestTable::iterator, bool> r =
258 m_readRequestTable.insert(RequestTable::value_type(line_addr, 0));
259
260 if (r.second) {
261 RequestTable::iterator i = r.first;
262 i->second = new SequencerRequest(pkt, request_type,
263 g_eventQueue_ptr->getTime());
264 m_outstanding_count++;
265 } else {
266 // There is an outstanding read request for the cache line
267 m_load_waiting_on_load_cycles++;
268 return RequestStatus_Aliased;
269 }
270 }
271
272 g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
273 assert(m_outstanding_count ==
274 (m_writeRequestTable.size() + m_readRequestTable.size()));
275
276 return RequestStatus_Ready;
277}
278
279void
280Sequencer::markRemoved()
281{
282 m_outstanding_count--;
283 assert(m_outstanding_count ==
284 m_writeRequestTable.size() + m_readRequestTable.size());
285}
286
287void
288Sequencer::removeRequest(SequencerRequest* srequest)
289{
290 assert(m_outstanding_count ==
291 m_writeRequestTable.size() + m_readRequestTable.size());
292
293 Address line_addr(srequest->pkt->getAddr());
294 line_addr.makeLineAddress();
295 if ((srequest->m_type == RubyRequestType_ST) ||
296 (srequest->m_type == RubyRequestType_RMW_Read) ||
297 (srequest->m_type == RubyRequestType_RMW_Write) ||
298 (srequest->m_type == RubyRequestType_Load_Linked) ||
299 (srequest->m_type == RubyRequestType_Store_Conditional) ||
300 (srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
301 (srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
302 m_writeRequestTable.erase(line_addr);
303 } else {
304 m_readRequestTable.erase(line_addr);
305 }
306
307 markRemoved();
308}
309
310bool
311Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
312{
313 //
314 // The success flag indicates whether the LLSC operation was successful.
315 // LL ops will always succeed, but SC may fail if the cache line is no
316 // longer locked.
317 //
318 bool success = true;
319 if (request->m_type == RubyRequestType_Store_Conditional) {
320 if (!m_dataCache_ptr->isLocked(address, m_version)) {
321 //
322 // For failed SC requests, indicate the failure to the cpu by
323 // setting the extra data to zero.
324 //
325 request->pkt->req->setExtraData(0);
326 success = false;
327 } else {
328 //
329 // For successful SC requests, indicate the success to the cpu by
330 // setting the extra data to one.
331 //
332 request->pkt->req->setExtraData(1);
333 }
334 //
335 // Independent of success, all SC operations must clear the lock
336 //
337 m_dataCache_ptr->clearLocked(address);
338 } else if (request->m_type == RubyRequestType_Load_Linked) {
339 //
340 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
341 // previously locked cache lines?
342 //
343 m_dataCache_ptr->setLocked(address, m_version);
344 } else if ((m_dataCache_ptr->isTagPresent(address)) &&
345 (m_dataCache_ptr->isLocked(address, m_version))) {
346 //
347 // Normal writes should clear the locked address
348 //
349 m_dataCache_ptr->clearLocked(address);
350 }
351 return success;
352}
353
354void
355Sequencer::writeCallback(const Address& address, DataBlock& data)
356{
357 writeCallback(address, GenericMachineType_NULL, data);
358}
359
360void
361Sequencer::writeCallback(const Address& address,
362 GenericMachineType mach,
363 DataBlock& data)
364{
365 writeCallback(address, mach, data, 0, 0, 0);
366}
367
368void
369Sequencer::writeCallback(const Address& address,
370 GenericMachineType mach,
371 DataBlock& data,
372 Time initialRequestTime,
373 Time forwardRequestTime,
374 Time firstResponseTime)
375{
376 assert(address == line_address(address));
377 assert(m_writeRequestTable.count(line_address(address)));
378
379 RequestTable::iterator i = m_writeRequestTable.find(address);
380 assert(i != m_writeRequestTable.end());
381 SequencerRequest* request = i->second;
382
383 m_writeRequestTable.erase(i);
384 markRemoved();
385
386 assert((request->m_type == RubyRequestType_ST) ||
387 (request->m_type == RubyRequestType_ATOMIC) ||
388 (request->m_type == RubyRequestType_RMW_Read) ||
389 (request->m_type == RubyRequestType_RMW_Write) ||
390 (request->m_type == RubyRequestType_Load_Linked) ||
391 (request->m_type == RubyRequestType_Store_Conditional) ||
392 (request->m_type == RubyRequestType_Locked_RMW_Read) ||
393 (request->m_type == RubyRequestType_Locked_RMW_Write) ||
394 (request->m_type == RubyRequestType_FLUSH));
395
396
397 //
398 // For Alpha, properly handle LL, SC, and write requests with respect to
399 // locked cache blocks.
400 //
401 // Not valid for Network_test protocl
402 //
403 bool success = true;
404 if(!m_usingNetworkTester)
405 success = handleLlsc(address, request);
406
407 if (request->m_type == RubyRequestType_Locked_RMW_Read) {
408 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
409 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
410 m_controller->unblock(address);
411 }
412
413 hitCallback(request, mach, data, success,
414 initialRequestTime, forwardRequestTime, firstResponseTime);
415}
416
417void
418Sequencer::readCallback(const Address& address, DataBlock& data)
419{
420 readCallback(address, GenericMachineType_NULL, data);
421}
422
423void
424Sequencer::readCallback(const Address& address,
425 GenericMachineType mach,
426 DataBlock& data)
427{
428 readCallback(address, mach, data, 0, 0, 0);
429}
430
431void
432Sequencer::readCallback(const Address& address,
433 GenericMachineType mach,
434 DataBlock& data,
435 Time initialRequestTime,
436 Time forwardRequestTime,
437 Time firstResponseTime)
438{
439 assert(address == line_address(address));
440 assert(m_readRequestTable.count(line_address(address)));
441
442 RequestTable::iterator i = m_readRequestTable.find(address);
443 assert(i != m_readRequestTable.end());
444 SequencerRequest* request = i->second;
445
446 m_readRequestTable.erase(i);
447 markRemoved();
448
449 assert((request->m_type == RubyRequestType_LD) ||
450 (request->m_type == RubyRequestType_IFETCH));
451
452 hitCallback(request, mach, data, true,
453 initialRequestTime, forwardRequestTime, firstResponseTime);
454}
455
456void
457Sequencer::hitCallback(SequencerRequest* srequest,
458 GenericMachineType mach,
459 DataBlock& data,
460 bool success,
461 Time initialRequestTime,
462 Time forwardRequestTime,
463 Time firstResponseTime)
464{
465 PacketPtr pkt = srequest->pkt;
466 Address request_address(pkt->getAddr());
467 Address request_line_address(pkt->getAddr());
468 request_line_address.makeLineAddress();
469 RubyRequestType type = srequest->m_type;
470 Time issued_time = srequest->issue_time;
471
472 // Set this cache entry to the most recently used
473 if (type == RubyRequestType_IFETCH) {
474 m_instCache_ptr->setMRU(request_line_address);
475 } else {
476 m_dataCache_ptr->setMRU(request_line_address);
477 }
478
479 assert(g_eventQueue_ptr->getTime() >= issued_time);
480 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
481
482 // Profile the miss latency for all non-zero demand misses
483 if (miss_latency != 0) {
484 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
485
486 if (mach == GenericMachineType_L1Cache_wCC) {
487 g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
488 initialRequestTime,
489 forwardRequestTime,
490 firstResponseTime,
491 g_eventQueue_ptr->getTime());
492 }
493
494 if (mach == GenericMachineType_Directory) {
495 g_system_ptr->getProfiler()->missLatencyDir(issued_time,
496 initialRequestTime,
497 forwardRequestTime,
498 firstResponseTime,
499 g_eventQueue_ptr->getTime());
500 }
501
502 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
503 curTick(), m_version, "Seq",
504 success ? "Done" : "SC_Failed", "", "",
505 request_address, miss_latency);
506 }
507
508 // update the data
509 if (g_system_ptr->m_warmup_enabled) {
510 assert(pkt->getPtr<uint8_t>(false) != NULL);
511 data.setData(pkt->getPtr<uint8_t>(false),
512 request_address.getOffset(), pkt->getSize());
513 } else if (pkt->getPtr<uint8_t>(true) != NULL) {
514 if ((type == RubyRequestType_LD) ||
515 (type == RubyRequestType_IFETCH) ||
516 (type == RubyRequestType_RMW_Read) ||
517 (type == RubyRequestType_Locked_RMW_Read) ||
518 (type == RubyRequestType_Load_Linked)) {
519 memcpy(pkt->getPtr<uint8_t>(true),
520 data.getData(request_address.getOffset(), pkt->getSize()),
521 pkt->getSize());
522 } else {
523 data.setData(pkt->getPtr<uint8_t>(true),
524 request_address.getOffset(), pkt->getSize());
525 }
526 } else {
527 DPRINTF(MemoryAccess,
528 "WARNING. Data not transfered from Ruby to M5 for type %s\n",
529 RubyRequestType_to_string(type));
530 }
531
532 // If using the RubyTester, update the RubyTester sender state's
533 // subBlock with the recieved data. The tester will later access
534 // this state.
535 // Note: RubyPort will access it's sender state before the
536 // RubyTester.
537 if (m_usingRubyTester) {
538 RubyPort::SenderState *requestSenderState =
539 safe_cast<RubyPort::SenderState*>(pkt->senderState);
540 RubyTester::SenderState* testerSenderState =
541 safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
542 testerSenderState->subBlock->mergeFrom(data);
543 }
544
545 delete srequest;
546
547 if (g_system_ptr->m_warmup_enabled) {
548 delete pkt;
549 g_system_ptr->m_cache_recorder->enqueueNextFetchRequest();
550 } else if (g_system_ptr->m_cooldown_enabled) {
551 delete pkt;
552 g_system_ptr->m_cache_recorder->enqueueNextFlushRequest();
553 } else {
554 ruby_hit_callback(pkt);
555 }
556}
557
558bool
559Sequencer::empty() const
560{
561 return m_writeRequestTable.empty() && m_readRequestTable.empty();
562}
563
564RequestStatus
565Sequencer::makeRequest(PacketPtr pkt)
566{
567 if (m_outstanding_count >= m_max_outstanding_requests) {
568 return RequestStatus_BufferFull;
569 }
570
571 RubyRequestType primary_type = RubyRequestType_NULL;
572 RubyRequestType secondary_type = RubyRequestType_NULL;
573
574 if (pkt->isLLSC()) {
575 //
576 // Alpha LL/SC instructions need to be handled carefully by the cache
577 // coherence protocol to ensure they follow the proper semantics. In
578 // particular, by identifying the operations as atomic, the protocol
579 // should understand that migratory sharing optimizations should not
580 // be performed (i.e. a load between the LL and SC should not steal
581 // away exclusive permission).
582 //
583 if (pkt->isWrite()) {
584 DPRINTF(RubySequencer, "Issuing SC\n");
585 primary_type = RubyRequestType_Store_Conditional;
586 } else {
587 DPRINTF(RubySequencer, "Issuing LL\n");
588 assert(pkt->isRead());
589 primary_type = RubyRequestType_Load_Linked;
590 }
591 secondary_type = RubyRequestType_ATOMIC;
592 } else if (pkt->req->isLocked()) {
593 //
594 // x86 locked instructions are translated to store cache coherence
595 // requests because these requests should always be treated as read
596 // exclusive operations and should leverage any migratory sharing
597 // optimization built into the protocol.
598 //
599 if (pkt->isWrite()) {
600 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
601 primary_type = RubyRequestType_Locked_RMW_Write;
602 } else {
603 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
604 assert(pkt->isRead());
605 primary_type = RubyRequestType_Locked_RMW_Read;
606 }
607 secondary_type = RubyRequestType_ST;
608 } else {
609 if (pkt->isRead()) {
610 if (pkt->req->isInstFetch()) {
611 primary_type = secondary_type = RubyRequestType_IFETCH;
612 } else {
613#if THE_ISA == X86_ISA
614 uint32_t flags = pkt->req->getFlags();
615 bool storeCheck = flags &
616 (TheISA::StoreCheck << TheISA::FlagShift);
617#else
618 bool storeCheck = false;
619#endif // X86_ISA
620 if (storeCheck) {
621 primary_type = RubyRequestType_RMW_Read;
622 secondary_type = RubyRequestType_ST;
623 } else {
624 primary_type = secondary_type = RubyRequestType_LD;
625 }
626 }
627 } else if (pkt->isWrite()) {
628 //
629 // Note: M5 packets do not differentiate ST from RMW_Write
630 //
631 primary_type = secondary_type = RubyRequestType_ST;
632 } else if (pkt->isFlush()) {
633 primary_type = secondary_type = RubyRequestType_FLUSH;
634 } else {
635 panic("Unsupported ruby packet type\n");
636 }
637 }
638
639 RequestStatus status = insertRequest(pkt, primary_type);
640 if (status != RequestStatus_Ready)
641 return status;
642
643 issueRequest(pkt, secondary_type);
644
645 // TODO: issue hardware prefetches here
646 return RequestStatus_Issued;
647}
648
649void
650Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
651{
652 int proc_id = -1;
653 if (pkt != NULL && pkt->req->hasContextId()) {
654 proc_id = pkt->req->contextId();
655 }
656
657 // If valid, copy the pc to the ruby request
658 Addr pc = 0;
659 if (pkt->req->hasPC()) {
660 pc = pkt->req->getPC();
661 }
662
663 RubyRequest *msg = new RubyRequest(pkt->getAddr(),
664 pkt->getPtr<uint8_t>(true),
665 pkt->getSize(), pc, secondary_type,
666 RubyAccessMode_Supervisor, pkt,
667 PrefetchBit_No, proc_id);
668
669 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
670 curTick(), m_version, "Seq", "Begin", "", "",
671 msg->getPhysicalAddress(),
672 RubyRequestType_to_string(secondary_type));
673
674 Time latency = 0; // initialzed to an null value
675
676 if (secondary_type == RubyRequestType_IFETCH)
677 latency = m_instCache_ptr->getLatency();
678 else
679 latency = m_dataCache_ptr->getLatency();
680
681 // Send the message to the cache controller
682 assert(latency > 0);
683
684 assert(m_mandatory_q_ptr != NULL);
685 m_mandatory_q_ptr->enqueue(msg, latency);
686}
687
688template <class KEY, class VALUE>
689std::ostream &
690operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
691{
692 typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
693 typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
694
695 out << "[";
696 for (; i != end; ++i)
697 out << " " << i->first << "=" << i->second;
698 out << " ]";
699
700 return out;
701}
702
703void
704Sequencer::print(ostream& out) const
705{
706 out << "[Sequencer: " << m_version
707 << ", outstanding requests: " << m_outstanding_count
708 << ", read request table: " << m_readRequestTable
709 << ", write request table: " << m_writeRequestTable
710 << "]";
711}
712
713// this can be called from setState whenever coherence permissions are
714// upgraded when invoked, coherence violations will be checked for the
715// given block
716void
717Sequencer::checkCoherence(const Address& addr)
718{
719#ifdef CHECK_COHERENCE
720 g_system_ptr->checkGlobalCoherenceInvariant(addr);
721#endif
722}
723
724void
725Sequencer::recordRequestType(SequencerRequestType requestType) {
726 DPRINTF(RubyStats, "Recorded statistic: %s\n",
727 SequencerRequestType_to_string(requestType));
728}
729
730
731void
732Sequencer::evictionCallback(const Address& address)
733{
734 ruby_eviction_callback(address);
735}
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "base/misc.hh"
30#include "base/str.hh"
31#include "config/the_isa.hh"
32#if THE_ISA == X86_ISA
33#include "arch/x86/insts/microldstop.hh"
34#endif // X86_ISA
35#include "cpu/testers/rubytest/RubyTester.hh"
36#include "debug/MemoryAccess.hh"
37#include "debug/ProtocolTrace.hh"
38#include "debug/RubySequencer.hh"
39#include "debug/RubyStats.hh"
40#include "mem/protocol/PrefetchBit.hh"
41#include "mem/protocol/RubyAccessMode.hh"
42#include "mem/ruby/buffers/MessageBuffer.hh"
43#include "mem/ruby/common/Global.hh"
44#include "mem/ruby/profiler/Profiler.hh"
45#include "mem/ruby/slicc_interface/RubyRequest.hh"
46#include "mem/ruby/system/CacheMemory.hh"
47#include "mem/ruby/system/Sequencer.hh"
48#include "mem/ruby/system/System.hh"
49#include "mem/packet.hh"
50#include "params/RubySequencer.hh"
51
52using namespace std;
53
54Sequencer *
55RubySequencerParams::create()
56{
57 return new Sequencer(this);
58}
59
60Sequencer::Sequencer(const Params *p)
61 : RubyPort(p), deadlockCheckEvent(this)
62{
63 m_store_waiting_on_load_cycles = 0;
64 m_store_waiting_on_store_cycles = 0;
65 m_load_waiting_on_store_cycles = 0;
66 m_load_waiting_on_load_cycles = 0;
67
68 m_outstanding_count = 0;
69
70 m_instCache_ptr = p->icache;
71 m_dataCache_ptr = p->dcache;
72 m_max_outstanding_requests = p->max_outstanding_requests;
73 m_deadlock_threshold = p->deadlock_threshold;
74
75 assert(m_max_outstanding_requests > 0);
76 assert(m_deadlock_threshold > 0);
77 assert(m_instCache_ptr != NULL);
78 assert(m_dataCache_ptr != NULL);
79
80 m_usingNetworkTester = p->using_network_tester;
81}
82
83Sequencer::~Sequencer()
84{
85}
86
87void
88Sequencer::wakeup()
89{
90 // Check for deadlock of any of the requests
91 Time current_time = g_eventQueue_ptr->getTime();
92
93 // Check across all outstanding requests
94 int total_outstanding = 0;
95
96 RequestTable::iterator read = m_readRequestTable.begin();
97 RequestTable::iterator read_end = m_readRequestTable.end();
98 for (; read != read_end; ++read) {
99 SequencerRequest* request = read->second;
100 if (current_time - request->issue_time < m_deadlock_threshold)
101 continue;
102
103 panic("Possible Deadlock detected. Aborting!\n"
104 "version: %d request.paddr: 0x%x m_readRequestTable: %d "
105 "current time: %u issue_time: %d difference: %d\n", m_version,
106 Address(request->pkt->getAddr()), m_readRequestTable.size(),
107 current_time, request->issue_time,
108 current_time - request->issue_time);
109 }
110
111 RequestTable::iterator write = m_writeRequestTable.begin();
112 RequestTable::iterator write_end = m_writeRequestTable.end();
113 for (; write != write_end; ++write) {
114 SequencerRequest* request = write->second;
115 if (current_time - request->issue_time < m_deadlock_threshold)
116 continue;
117
118 panic("Possible Deadlock detected. Aborting!\n"
119 "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
120 "current time: %u issue_time: %d difference: %d\n", m_version,
121 Address(request->pkt->getAddr()), m_writeRequestTable.size(),
122 current_time, request->issue_time,
123 current_time - request->issue_time);
124 }
125
126 total_outstanding += m_writeRequestTable.size();
127 total_outstanding += m_readRequestTable.size();
128
129 assert(m_outstanding_count == total_outstanding);
130
131 if (m_outstanding_count > 0) {
132 // If there are still outstanding requests, keep checking
133 schedule(deadlockCheckEvent,
134 m_deadlock_threshold * g_eventQueue_ptr->getClock() +
135 curTick());
136 }
137}
138
139void
140Sequencer::printStats(ostream & out) const
141{
142 out << "Sequencer: " << m_name << endl
143 << " store_waiting_on_load_cycles: "
144 << m_store_waiting_on_load_cycles << endl
145 << " store_waiting_on_store_cycles: "
146 << m_store_waiting_on_store_cycles << endl
147 << " load_waiting_on_load_cycles: "
148 << m_load_waiting_on_load_cycles << endl
149 << " load_waiting_on_store_cycles: "
150 << m_load_waiting_on_store_cycles << endl;
151}
152
153void
154Sequencer::printProgress(ostream& out) const
155{
156#if 0
157 int total_demand = 0;
158 out << "Sequencer Stats Version " << m_version << endl;
159 out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
160 out << "---------------" << endl;
161 out << "outstanding requests" << endl;
162
163 out << "proc " << m_Read
164 << " version Requests = " << m_readRequestTable.size() << endl;
165
166 // print the request table
167 RequestTable::iterator read = m_readRequestTable.begin();
168 RequestTable::iterator read_end = m_readRequestTable.end();
169 for (; read != read_end; ++read) {
170 SequencerRequest* request = read->second;
171 out << "\tRequest[ " << i << " ] = " << request->type
172 << " Address " << rkeys[i]
173 << " Posted " << request->issue_time
174 << " PF " << PrefetchBit_No << endl;
175 total_demand++;
176 }
177
178 out << "proc " << m_version
179 << " Write Requests = " << m_writeRequestTable.size << endl;
180
181 // print the request table
182 RequestTable::iterator write = m_writeRequestTable.begin();
183 RequestTable::iterator write_end = m_writeRequestTable.end();
184 for (; write != write_end; ++write) {
185 SequencerRequest* request = write->second;
186 out << "\tRequest[ " << i << " ] = " << request.getType()
187 << " Address " << wkeys[i]
188 << " Posted " << request.getTime()
189 << " PF " << request.getPrefetch() << endl;
190 if (request.getPrefetch() == PrefetchBit_No) {
191 total_demand++;
192 }
193 }
194
195 out << endl;
196
197 out << "Total Number Outstanding: " << m_outstanding_count << endl
198 << "Total Number Demand : " << total_demand << endl
199 << "Total Number Prefetches : " << m_outstanding_count - total_demand
200 << endl << endl << endl;
201#endif
202}
203
204// Insert the request on the correct request table. Return true if
205// the entry was already present.
206RequestStatus
207Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
208{
209 assert(m_outstanding_count ==
210 (m_writeRequestTable.size() + m_readRequestTable.size()));
211
212 // See if we should schedule a deadlock check
213 if (deadlockCheckEvent.scheduled() == false) {
214 schedule(deadlockCheckEvent,
215 m_deadlock_threshold * g_eventQueue_ptr->getClock()
216 + curTick());
217 }
218
219 Address line_addr(pkt->getAddr());
220 line_addr.makeLineAddress();
221 if ((request_type == RubyRequestType_ST) ||
222 (request_type == RubyRequestType_RMW_Read) ||
223 (request_type == RubyRequestType_RMW_Write) ||
224 (request_type == RubyRequestType_Load_Linked) ||
225 (request_type == RubyRequestType_Store_Conditional) ||
226 (request_type == RubyRequestType_Locked_RMW_Read) ||
227 (request_type == RubyRequestType_Locked_RMW_Write) ||
228 (request_type == RubyRequestType_FLUSH)) {
229
230 // Check if there is any outstanding read request for the same
231 // cache line.
232 if (m_readRequestTable.count(line_addr) > 0) {
233 m_store_waiting_on_load_cycles++;
234 return RequestStatus_Aliased;
235 }
236
237 pair<RequestTable::iterator, bool> r =
238 m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0));
239 if (r.second) {
240 RequestTable::iterator i = r.first;
241 i->second = new SequencerRequest(pkt, request_type,
242 g_eventQueue_ptr->getTime());
243 m_outstanding_count++;
244 } else {
245 // There is an outstanding write request for the cache line
246 m_store_waiting_on_store_cycles++;
247 return RequestStatus_Aliased;
248 }
249 } else {
250 // Check if there is any outstanding write request for the same
251 // cache line.
252 if (m_writeRequestTable.count(line_addr) > 0) {
253 m_load_waiting_on_store_cycles++;
254 return RequestStatus_Aliased;
255 }
256
257 pair<RequestTable::iterator, bool> r =
258 m_readRequestTable.insert(RequestTable::value_type(line_addr, 0));
259
260 if (r.second) {
261 RequestTable::iterator i = r.first;
262 i->second = new SequencerRequest(pkt, request_type,
263 g_eventQueue_ptr->getTime());
264 m_outstanding_count++;
265 } else {
266 // There is an outstanding read request for the cache line
267 m_load_waiting_on_load_cycles++;
268 return RequestStatus_Aliased;
269 }
270 }
271
272 g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
273 assert(m_outstanding_count ==
274 (m_writeRequestTable.size() + m_readRequestTable.size()));
275
276 return RequestStatus_Ready;
277}
278
279void
280Sequencer::markRemoved()
281{
282 m_outstanding_count--;
283 assert(m_outstanding_count ==
284 m_writeRequestTable.size() + m_readRequestTable.size());
285}
286
287void
288Sequencer::removeRequest(SequencerRequest* srequest)
289{
290 assert(m_outstanding_count ==
291 m_writeRequestTable.size() + m_readRequestTable.size());
292
293 Address line_addr(srequest->pkt->getAddr());
294 line_addr.makeLineAddress();
295 if ((srequest->m_type == RubyRequestType_ST) ||
296 (srequest->m_type == RubyRequestType_RMW_Read) ||
297 (srequest->m_type == RubyRequestType_RMW_Write) ||
298 (srequest->m_type == RubyRequestType_Load_Linked) ||
299 (srequest->m_type == RubyRequestType_Store_Conditional) ||
300 (srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
301 (srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
302 m_writeRequestTable.erase(line_addr);
303 } else {
304 m_readRequestTable.erase(line_addr);
305 }
306
307 markRemoved();
308}
309
310bool
311Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
312{
313 //
314 // The success flag indicates whether the LLSC operation was successful.
315 // LL ops will always succeed, but SC may fail if the cache line is no
316 // longer locked.
317 //
318 bool success = true;
319 if (request->m_type == RubyRequestType_Store_Conditional) {
320 if (!m_dataCache_ptr->isLocked(address, m_version)) {
321 //
322 // For failed SC requests, indicate the failure to the cpu by
323 // setting the extra data to zero.
324 //
325 request->pkt->req->setExtraData(0);
326 success = false;
327 } else {
328 //
329 // For successful SC requests, indicate the success to the cpu by
330 // setting the extra data to one.
331 //
332 request->pkt->req->setExtraData(1);
333 }
334 //
335 // Independent of success, all SC operations must clear the lock
336 //
337 m_dataCache_ptr->clearLocked(address);
338 } else if (request->m_type == RubyRequestType_Load_Linked) {
339 //
340 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
341 // previously locked cache lines?
342 //
343 m_dataCache_ptr->setLocked(address, m_version);
344 } else if ((m_dataCache_ptr->isTagPresent(address)) &&
345 (m_dataCache_ptr->isLocked(address, m_version))) {
346 //
347 // Normal writes should clear the locked address
348 //
349 m_dataCache_ptr->clearLocked(address);
350 }
351 return success;
352}
353
354void
355Sequencer::writeCallback(const Address& address, DataBlock& data)
356{
357 writeCallback(address, GenericMachineType_NULL, data);
358}
359
360void
361Sequencer::writeCallback(const Address& address,
362 GenericMachineType mach,
363 DataBlock& data)
364{
365 writeCallback(address, mach, data, 0, 0, 0);
366}
367
368void
369Sequencer::writeCallback(const Address& address,
370 GenericMachineType mach,
371 DataBlock& data,
372 Time initialRequestTime,
373 Time forwardRequestTime,
374 Time firstResponseTime)
375{
376 assert(address == line_address(address));
377 assert(m_writeRequestTable.count(line_address(address)));
378
379 RequestTable::iterator i = m_writeRequestTable.find(address);
380 assert(i != m_writeRequestTable.end());
381 SequencerRequest* request = i->second;
382
383 m_writeRequestTable.erase(i);
384 markRemoved();
385
386 assert((request->m_type == RubyRequestType_ST) ||
387 (request->m_type == RubyRequestType_ATOMIC) ||
388 (request->m_type == RubyRequestType_RMW_Read) ||
389 (request->m_type == RubyRequestType_RMW_Write) ||
390 (request->m_type == RubyRequestType_Load_Linked) ||
391 (request->m_type == RubyRequestType_Store_Conditional) ||
392 (request->m_type == RubyRequestType_Locked_RMW_Read) ||
393 (request->m_type == RubyRequestType_Locked_RMW_Write) ||
394 (request->m_type == RubyRequestType_FLUSH));
395
396
397 //
398 // For Alpha, properly handle LL, SC, and write requests with respect to
399 // locked cache blocks.
400 //
401 // Not valid for Network_test protocl
402 //
403 bool success = true;
404 if(!m_usingNetworkTester)
405 success = handleLlsc(address, request);
406
407 if (request->m_type == RubyRequestType_Locked_RMW_Read) {
408 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
409 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
410 m_controller->unblock(address);
411 }
412
413 hitCallback(request, mach, data, success,
414 initialRequestTime, forwardRequestTime, firstResponseTime);
415}
416
417void
418Sequencer::readCallback(const Address& address, DataBlock& data)
419{
420 readCallback(address, GenericMachineType_NULL, data);
421}
422
423void
424Sequencer::readCallback(const Address& address,
425 GenericMachineType mach,
426 DataBlock& data)
427{
428 readCallback(address, mach, data, 0, 0, 0);
429}
430
431void
432Sequencer::readCallback(const Address& address,
433 GenericMachineType mach,
434 DataBlock& data,
435 Time initialRequestTime,
436 Time forwardRequestTime,
437 Time firstResponseTime)
438{
439 assert(address == line_address(address));
440 assert(m_readRequestTable.count(line_address(address)));
441
442 RequestTable::iterator i = m_readRequestTable.find(address);
443 assert(i != m_readRequestTable.end());
444 SequencerRequest* request = i->second;
445
446 m_readRequestTable.erase(i);
447 markRemoved();
448
449 assert((request->m_type == RubyRequestType_LD) ||
450 (request->m_type == RubyRequestType_IFETCH));
451
452 hitCallback(request, mach, data, true,
453 initialRequestTime, forwardRequestTime, firstResponseTime);
454}
455
456void
457Sequencer::hitCallback(SequencerRequest* srequest,
458 GenericMachineType mach,
459 DataBlock& data,
460 bool success,
461 Time initialRequestTime,
462 Time forwardRequestTime,
463 Time firstResponseTime)
464{
465 PacketPtr pkt = srequest->pkt;
466 Address request_address(pkt->getAddr());
467 Address request_line_address(pkt->getAddr());
468 request_line_address.makeLineAddress();
469 RubyRequestType type = srequest->m_type;
470 Time issued_time = srequest->issue_time;
471
472 // Set this cache entry to the most recently used
473 if (type == RubyRequestType_IFETCH) {
474 m_instCache_ptr->setMRU(request_line_address);
475 } else {
476 m_dataCache_ptr->setMRU(request_line_address);
477 }
478
479 assert(g_eventQueue_ptr->getTime() >= issued_time);
480 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
481
482 // Profile the miss latency for all non-zero demand misses
483 if (miss_latency != 0) {
484 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
485
486 if (mach == GenericMachineType_L1Cache_wCC) {
487 g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
488 initialRequestTime,
489 forwardRequestTime,
490 firstResponseTime,
491 g_eventQueue_ptr->getTime());
492 }
493
494 if (mach == GenericMachineType_Directory) {
495 g_system_ptr->getProfiler()->missLatencyDir(issued_time,
496 initialRequestTime,
497 forwardRequestTime,
498 firstResponseTime,
499 g_eventQueue_ptr->getTime());
500 }
501
502 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
503 curTick(), m_version, "Seq",
504 success ? "Done" : "SC_Failed", "", "",
505 request_address, miss_latency);
506 }
507
508 // update the data
509 if (g_system_ptr->m_warmup_enabled) {
510 assert(pkt->getPtr<uint8_t>(false) != NULL);
511 data.setData(pkt->getPtr<uint8_t>(false),
512 request_address.getOffset(), pkt->getSize());
513 } else if (pkt->getPtr<uint8_t>(true) != NULL) {
514 if ((type == RubyRequestType_LD) ||
515 (type == RubyRequestType_IFETCH) ||
516 (type == RubyRequestType_RMW_Read) ||
517 (type == RubyRequestType_Locked_RMW_Read) ||
518 (type == RubyRequestType_Load_Linked)) {
519 memcpy(pkt->getPtr<uint8_t>(true),
520 data.getData(request_address.getOffset(), pkt->getSize()),
521 pkt->getSize());
522 } else {
523 data.setData(pkt->getPtr<uint8_t>(true),
524 request_address.getOffset(), pkt->getSize());
525 }
526 } else {
527 DPRINTF(MemoryAccess,
528 "WARNING. Data not transfered from Ruby to M5 for type %s\n",
529 RubyRequestType_to_string(type));
530 }
531
532 // If using the RubyTester, update the RubyTester sender state's
533 // subBlock with the recieved data. The tester will later access
534 // this state.
535 // Note: RubyPort will access it's sender state before the
536 // RubyTester.
537 if (m_usingRubyTester) {
538 RubyPort::SenderState *requestSenderState =
539 safe_cast<RubyPort::SenderState*>(pkt->senderState);
540 RubyTester::SenderState* testerSenderState =
541 safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
542 testerSenderState->subBlock->mergeFrom(data);
543 }
544
545 delete srequest;
546
547 if (g_system_ptr->m_warmup_enabled) {
548 delete pkt;
549 g_system_ptr->m_cache_recorder->enqueueNextFetchRequest();
550 } else if (g_system_ptr->m_cooldown_enabled) {
551 delete pkt;
552 g_system_ptr->m_cache_recorder->enqueueNextFlushRequest();
553 } else {
554 ruby_hit_callback(pkt);
555 }
556}
557
558bool
559Sequencer::empty() const
560{
561 return m_writeRequestTable.empty() && m_readRequestTable.empty();
562}
563
564RequestStatus
565Sequencer::makeRequest(PacketPtr pkt)
566{
567 if (m_outstanding_count >= m_max_outstanding_requests) {
568 return RequestStatus_BufferFull;
569 }
570
571 RubyRequestType primary_type = RubyRequestType_NULL;
572 RubyRequestType secondary_type = RubyRequestType_NULL;
573
574 if (pkt->isLLSC()) {
575 //
576 // Alpha LL/SC instructions need to be handled carefully by the cache
577 // coherence protocol to ensure they follow the proper semantics. In
578 // particular, by identifying the operations as atomic, the protocol
579 // should understand that migratory sharing optimizations should not
580 // be performed (i.e. a load between the LL and SC should not steal
581 // away exclusive permission).
582 //
583 if (pkt->isWrite()) {
584 DPRINTF(RubySequencer, "Issuing SC\n");
585 primary_type = RubyRequestType_Store_Conditional;
586 } else {
587 DPRINTF(RubySequencer, "Issuing LL\n");
588 assert(pkt->isRead());
589 primary_type = RubyRequestType_Load_Linked;
590 }
591 secondary_type = RubyRequestType_ATOMIC;
592 } else if (pkt->req->isLocked()) {
593 //
594 // x86 locked instructions are translated to store cache coherence
595 // requests because these requests should always be treated as read
596 // exclusive operations and should leverage any migratory sharing
597 // optimization built into the protocol.
598 //
599 if (pkt->isWrite()) {
600 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
601 primary_type = RubyRequestType_Locked_RMW_Write;
602 } else {
603 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
604 assert(pkt->isRead());
605 primary_type = RubyRequestType_Locked_RMW_Read;
606 }
607 secondary_type = RubyRequestType_ST;
608 } else {
609 if (pkt->isRead()) {
610 if (pkt->req->isInstFetch()) {
611 primary_type = secondary_type = RubyRequestType_IFETCH;
612 } else {
613#if THE_ISA == X86_ISA
614 uint32_t flags = pkt->req->getFlags();
615 bool storeCheck = flags &
616 (TheISA::StoreCheck << TheISA::FlagShift);
617#else
618 bool storeCheck = false;
619#endif // X86_ISA
620 if (storeCheck) {
621 primary_type = RubyRequestType_RMW_Read;
622 secondary_type = RubyRequestType_ST;
623 } else {
624 primary_type = secondary_type = RubyRequestType_LD;
625 }
626 }
627 } else if (pkt->isWrite()) {
628 //
629 // Note: M5 packets do not differentiate ST from RMW_Write
630 //
631 primary_type = secondary_type = RubyRequestType_ST;
632 } else if (pkt->isFlush()) {
633 primary_type = secondary_type = RubyRequestType_FLUSH;
634 } else {
635 panic("Unsupported ruby packet type\n");
636 }
637 }
638
639 RequestStatus status = insertRequest(pkt, primary_type);
640 if (status != RequestStatus_Ready)
641 return status;
642
643 issueRequest(pkt, secondary_type);
644
645 // TODO: issue hardware prefetches here
646 return RequestStatus_Issued;
647}
648
649void
650Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
651{
652 int proc_id = -1;
653 if (pkt != NULL && pkt->req->hasContextId()) {
654 proc_id = pkt->req->contextId();
655 }
656
657 // If valid, copy the pc to the ruby request
658 Addr pc = 0;
659 if (pkt->req->hasPC()) {
660 pc = pkt->req->getPC();
661 }
662
663 RubyRequest *msg = new RubyRequest(pkt->getAddr(),
664 pkt->getPtr<uint8_t>(true),
665 pkt->getSize(), pc, secondary_type,
666 RubyAccessMode_Supervisor, pkt,
667 PrefetchBit_No, proc_id);
668
669 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
670 curTick(), m_version, "Seq", "Begin", "", "",
671 msg->getPhysicalAddress(),
672 RubyRequestType_to_string(secondary_type));
673
674 Time latency = 0; // initialzed to an null value
675
676 if (secondary_type == RubyRequestType_IFETCH)
677 latency = m_instCache_ptr->getLatency();
678 else
679 latency = m_dataCache_ptr->getLatency();
680
681 // Send the message to the cache controller
682 assert(latency > 0);
683
684 assert(m_mandatory_q_ptr != NULL);
685 m_mandatory_q_ptr->enqueue(msg, latency);
686}
687
688template <class KEY, class VALUE>
689std::ostream &
690operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
691{
692 typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
693 typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
694
695 out << "[";
696 for (; i != end; ++i)
697 out << " " << i->first << "=" << i->second;
698 out << " ]";
699
700 return out;
701}
702
703void
704Sequencer::print(ostream& out) const
705{
706 out << "[Sequencer: " << m_version
707 << ", outstanding requests: " << m_outstanding_count
708 << ", read request table: " << m_readRequestTable
709 << ", write request table: " << m_writeRequestTable
710 << "]";
711}
712
713// this can be called from setState whenever coherence permissions are
714// upgraded when invoked, coherence violations will be checked for the
715// given block
716void
717Sequencer::checkCoherence(const Address& addr)
718{
719#ifdef CHECK_COHERENCE
720 g_system_ptr->checkGlobalCoherenceInvariant(addr);
721#endif
722}
723
724void
725Sequencer::recordRequestType(SequencerRequestType requestType) {
726 DPRINTF(RubyStats, "Recorded statistic: %s\n",
727 SequencerRequestType_to_string(requestType));
728}
729
730
731void
732Sequencer::evictionCallback(const Address& address)
733{
734 ruby_eviction_callback(address);
735}