1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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50
51Sequencer *
52RubySequencerParams::create()
53{
54 return new Sequencer(this);
55}
56
57Sequencer::Sequencer(const Params *p)
58 : RubyPort(p), deadlockCheckEvent(this)
59{
60 m_store_waiting_on_load_cycles = 0;
61 m_store_waiting_on_store_cycles = 0;
62 m_load_waiting_on_store_cycles = 0;
63 m_load_waiting_on_load_cycles = 0;
64
65 m_outstanding_count = 0;
66
67 m_instCache_ptr = p->icache;
68 m_dataCache_ptr = p->dcache;
69 m_max_outstanding_requests = p->max_outstanding_requests;
70 m_deadlock_threshold = p->deadlock_threshold;
71
72 assert(m_max_outstanding_requests > 0);

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128 assert(m_outstanding_count == total_outstanding);
129
130 if (m_outstanding_count > 0) {
131 // If there are still outstanding requests, keep checking
132 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
133 }
134}
135
136void Sequencer::clearStats()
137{
138 m_outstandReqHist.clear();
139
140 // Initialize the histograms that track latency of all requests
141 m_latencyHist.clear(20);
142 m_typeLatencyHist.resize(RubyRequestType_NUM);
143 for (int i = 0; i < RubyRequestType_NUM; i++) {
144 m_typeLatencyHist[i].clear(20);
145 }
146
147 // Initialize the histograms that track latency of requests that
148 // hit in the cache attached to the sequencer.
149 m_hitLatencyHist.clear(20);
150 m_hitTypeLatencyHist.resize(RubyRequestType_NUM);
151 m_hitTypeMachLatencyHist.resize(RubyRequestType_NUM);
152
153 for (int i = 0; i < RubyRequestType_NUM; i++) {
154 m_hitTypeLatencyHist[i].clear(20);
155 m_hitTypeMachLatencyHist[i].resize(MachineType_NUM);
156 for (int j = 0; j < MachineType_NUM; j++) {
157 m_hitTypeMachLatencyHist[i][j].clear(20);
158 }
159 }
160
161 // Initialize the histograms that track the latency of requests that
162 // missed in the cache attached to the sequencer.
163 m_missLatencyHist.clear(20);
164 m_missTypeLatencyHist.resize(RubyRequestType_NUM);
165 m_missTypeMachLatencyHist.resize(RubyRequestType_NUM);
166
167 for (int i = 0; i < RubyRequestType_NUM; i++) {
168 m_missTypeLatencyHist[i].clear(20);
169 m_missTypeMachLatencyHist[i].resize(MachineType_NUM);
170 for (int j = 0; j < MachineType_NUM; j++) {
171 m_missTypeMachLatencyHist[i][j].clear(20);
172 }
173 }
174
175 m_hitMachLatencyHist.resize(MachineType_NUM);
176 m_missMachLatencyHist.resize(MachineType_NUM);
177 m_IssueToInitialDelayHist.resize(MachineType_NUM);
178 m_InitialToForwardDelayHist.resize(MachineType_NUM);
179 m_ForwardToFirstResponseDelayHist.resize(MachineType_NUM);
180 m_FirstResponseToCompletionDelayHist.resize(MachineType_NUM);
181 m_IncompleteTimes.resize(MachineType_NUM);
182
183 for (int i = 0; i < MachineType_NUM; i++) {
184 m_missMachLatencyHist[i].clear(20);
185 m_hitMachLatencyHist[i].clear(20);
186
187 m_IssueToInitialDelayHist[i].clear(20);
188 m_InitialToForwardDelayHist[i].clear(20);
189 m_ForwardToFirstResponseDelayHist[i].clear(20);
190 m_FirstResponseToCompletionDelayHist[i].clear(20);
191
192 m_IncompleteTimes[i] = 0;
193 }
194}
195
196void
197Sequencer::printStats(ostream & out) const
198{
199 out << "Sequencer: " << m_name << endl
200 << " store_waiting_on_load_cycles: "
201 << m_store_waiting_on_load_cycles << endl
202 << " store_waiting_on_store_cycles: "
203 << m_store_waiting_on_store_cycles << endl
204 << " load_waiting_on_load_cycles: "
205 << m_load_waiting_on_load_cycles << endl
206 << " load_waiting_on_store_cycles: "
207 << m_load_waiting_on_store_cycles << endl;
208}
209
210void
211Sequencer::printProgress(ostream& out) const
212{
213#if 0
214 int total_demand = 0;
215 out << "Sequencer Stats Version " << m_version << endl;
216 out << "Current time = " << g_system_ptr->getTime() << endl;
217 out << "---------------" << endl;
218 out << "outstanding requests" << endl;

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286 (request_type == RubyRequestType_Store_Conditional) ||
287 (request_type == RubyRequestType_Locked_RMW_Read) ||
288 (request_type == RubyRequestType_Locked_RMW_Write) ||
289 (request_type == RubyRequestType_FLUSH)) {
290
291 // Check if there is any outstanding read request for the same
292 // cache line.
293 if (m_readRequestTable.count(line_addr) > 0) {
294 m_store_waiting_on_load_cycles++;
295 return RequestStatus_Aliased;
296 }
297
298 pair<RequestTable::iterator, bool> r =
299 m_writeRequestTable.insert(default_entry);
300 if (r.second) {
301 RequestTable::iterator i = r.first;
302 i->second = new SequencerRequest(pkt, request_type, curCycle());
303 m_outstanding_count++;
304 } else {
305 // There is an outstanding write request for the cache line
306 m_store_waiting_on_store_cycles++;
307 return RequestStatus_Aliased;
308 }
309 } else {
310 // Check if there is any outstanding write request for the same
311 // cache line.
312 if (m_writeRequestTable.count(line_addr) > 0) {
313 m_load_waiting_on_store_cycles++;
314 return RequestStatus_Aliased;
315 }
316
317 pair<RequestTable::iterator, bool> r =
318 m_readRequestTable.insert(default_entry);
319
320 if (r.second) {
321 RequestTable::iterator i = r.first;
322 i->second = new SequencerRequest(pkt, request_type, curCycle());
323 m_outstanding_count++;
324 } else {
325 // There is an outstanding read request for the cache line
326 m_load_waiting_on_load_cycles++;
327 return RequestStatus_Aliased;
328 }
329 }
330
331 m_outstandReqHist.add(m_outstanding_count);
332 assert(m_outstanding_count ==
333 (m_writeRequestTable.size() + m_readRequestTable.size()));
334
335 return RequestStatus_Ready;
336}
337
338void
339Sequencer::markRemoved()

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427void
428Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type,
429 const MachineType respondingMach,
430 bool isExternalHit, Cycles issuedTime,
431 Cycles initialRequestTime,
432 Cycles forwardRequestTime,
433 Cycles firstResponseTime, Cycles completionTime)
434{
435 m_latencyHist.add(cycles);
436 m_typeLatencyHist[type].add(cycles);
437
438 if (isExternalHit) {
439 m_missLatencyHist.add(cycles);
440 m_missTypeLatencyHist[type].add(cycles);
441
442 if (respondingMach != MachineType_NUM) {
443 m_missMachLatencyHist[respondingMach].add(cycles);
444 m_missTypeMachLatencyHist[type][respondingMach].add(cycles);
445
446 if ((issuedTime <= initialRequestTime) &&
447 (initialRequestTime <= forwardRequestTime) &&
448 (forwardRequestTime <= firstResponseTime) &&
449 (firstResponseTime <= completionTime)) {
450
451 m_IssueToInitialDelayHist[respondingMach].add(
452 initialRequestTime - issuedTime);
453 m_InitialToForwardDelayHist[respondingMach].add(
454 forwardRequestTime - initialRequestTime);
455 m_ForwardToFirstResponseDelayHist[respondingMach].add(
456 firstResponseTime - forwardRequestTime);
457 m_FirstResponseToCompletionDelayHist[respondingMach].add(
458 completionTime - firstResponseTime);
459 } else {
460 m_IncompleteTimes[respondingMach]++;
461 }
462 }
463 } else {
464 m_hitLatencyHist.add(cycles);
465 m_hitTypeLatencyHist[type].add(cycles);
466
467 if (respondingMach != MachineType_NUM) {
468 m_hitMachLatencyHist[respondingMach].add(cycles);
469 m_hitTypeMachLatencyHist[type][respondingMach].add(cycles);
470 }
471 }
472}
473
474void
475Sequencer::writeCallback(const Address& address, DataBlock& data,
476 const bool externalHit, const MachineType mach,
477 const Cycles initialRequestTime,

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805}
806
807
808void
809Sequencer::evictionCallback(const Address& address)
810{
811 ruby_eviction_callback(address);
812}