1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 35 unchanged lines hidden (view full) ---

44
45//Sequencer::Sequencer(int core_id, MessageBuffer* mandatory_q)
46
47#define LLSC_FAIL -2
48long int already = 0;
49Sequencer::Sequencer(const string & name)
50 :RubyPort(name)
51{
52}
53
54void Sequencer::init(const vector<string> & argv)
55{
56 m_deadlock_check_scheduled = false;
57 m_outstanding_count = 0;
58
59 m_max_outstanding_requests = 0;

--- 78 unchanged lines hidden (view full) ---

138
139 if (m_outstanding_count > 0) { // If there are still outstanding requests, keep checking
140 g_eventQueue_ptr->scheduleEvent(this, m_deadlock_threshold);
141 } else {
142 m_deadlock_check_scheduled = false;
143 }
144}
145
146void Sequencer::printProgress(ostream& out) const{
147 /*
148 int total_demand = 0;
149 out << "Sequencer Stats Version " << m_version << endl;
150 out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
151 out << "---------------" << endl;
152 out << "outstanding requests" << endl;
153

--- 195 unchanged lines hidden (view full) ---

349 }
350
351 m_hit_callback(srequest->id);
352 delete srequest;
353}
354
355// Returns true if the sequencer already has a load or store outstanding
356int Sequencer::isReady(const RubyRequest& request) {
357 if( m_writeRequestTable.exist(line_address(Address(request.paddr))) ||
358 m_readRequestTable.exist(line_address(Address(request.paddr))) ){
359 return LIBRUBY_ALIASED_REQUEST;
360 }
361
362 if (m_outstanding_count >= m_max_outstanding_requests) {
363 return LIBRUBY_BUFFER_FULL;
364 }
365
366 return 1;
367}

--- 19 unchanged lines hidden (view full) ---

387 return LLSC_FAIL;
388 }
389 else {
390 m_dataCache_ptr->clearLocked(line_address(Address(request.paddr)));
391 }
392 }
393 issueRequest(request);
394
395 // TODO: issue hardware prefetches here
396 return id;
397 }
398 else {
399 assert(0);
400 }
401 }
402 else {
403 return ready;
404 }
405}
406
407void Sequencer::issueRequest(const RubyRequest& request) {
408
409 // TODO: get rid of CacheMsg, CacheRequestType, and AccessModeTYpe, & have SLICC use RubyRequest and subtypes natively
410 CacheRequestType ctype;

--- 132 unchanged lines hidden ---