1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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41#include "RubyConfig.hh"
42//#include "Tracer.hh"
43#include "AbstractChip.hh"
44#include "Chip.hh"
45#include "Tester.hh"
46#include "SubBlock.hh"
47#include "Protocol.hh"
48#include "Map.hh"
49#include "interface.hh"
50
51Sequencer::Sequencer(AbstractChip* chip_ptr, int version) {
52 m_chip_ptr = chip_ptr;
53 m_version = version;
54
55 m_deadlock_check_scheduled = false;
56 m_outstanding_count = 0;
57

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592 g_system_ptr->getProfiler()->swPrefetchLatency(miss_latency, type, respondingMach);
593 return; // Ignore the software prefetch, don't callback the driver
594 }
595
596 // Profile the miss latency for all non-zero demand misses
597 if (miss_latency != 0) {
598 g_system_ptr->getProfiler()->missLatency(miss_latency, type, respondingMach);
599
600#if 0
601 uinteger_t tick = SIMICS_read_control_register(m_version, SIMICS_get_register_number(m_version, "tick"));
602 uinteger_t tick_cmpr = SIMICS_read_control_register(m_version, SIMICS_get_register_number(m_version, "tick_cmpr"));
603 uinteger_t stick = SIMICS_read_control_register(m_version, SIMICS_get_register_number(m_version, "stick"));
604 uinteger_t stick_cmpr = SIMICS_read_control_register(m_version, SIMICS_get_register_number(m_version, "stick_cmpr"));
605 cout << "END PROC " << m_version << hex << " tick = " << tick << " tick_cmpr = " << tick_cmpr << " stick = " << stick << " stick_cmpr = " << stick_cmpr << " cycle = "<< g_eventQueue_ptr->getTime() << dec << endl;
606#endif
607
608 }
609
610 bool write =
611 (type == CacheRequestType_ST) ||
612 (type == CacheRequestType_ATOMIC);
613
614 if (TSO && write) {
615 m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->callBack(line_address(request.getAddress()), data);
616 } else {
617
618 // Copy the correct bytes out of the cache line into the subblock
619 SubBlock subblock(request_address, request_logical_address, size);
620 subblock.mergeFrom(data); // copy the correct bytes from DataBlock in the SubBlock
621
622 // Scan the store buffer to see if there are any outstanding stores we need to collect
623 if (TSO) {
624 m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->updateSubBlock(subblock);
625 }
626
627 // Call into the Driver (Tester or Simics) and let it read and/or modify the sub-block
628 g_system_ptr->getDriver()->hitCallback(m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version, subblock, type, threadID);
629
630 // If the request was a Store or Atomic, apply the changes in the SubBlock to the DataBlock
631 // (This is only triggered for the non-TSO case)
632 if (write) {
633 assert(!TSO);
634 subblock.mergeTo(data); // copy the correct bytes from SubBlock into the DataBlock
635 }
636 }
637}
638
639void Sequencer::printDebug(){
640 //notify driver of debug
641 g_system_ptr->getDriver()->printDebug();
642}
643
644// Returns true if the sequencer already has a load or store outstanding
645bool
646Sequencer::isReady(const Packet* pkt) const

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705 }
706
707 if (TSO) {
708 return m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->isReady();
709 }
710 return true;
711}
712
713// Called by Driver (Simics or Tester).
714void
715Sequencer::makeRequest(const Packet* pkt, void* data)
716{
717 int cpu_number = pkt->req->contextId();
718 la_t logical_addr = pkt->req->getVaddr();
719 pa_t physical_addr = pkt->req->getPaddr();
720 int request_size = pkt->getSize();
721 CacheRequestType type_of_request;

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781 data_ptr);
782
783 if (hit && (request.getType() == CacheRequestType_IFETCH || !REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH) ) {
784 DEBUG_MSG(SEQUENCER_COMP, MedPrio, "Fast path hit");
785 hitCallback(request, *data_ptr, GenericMachineType_L1Cache, thread);
786 return true;
787 }
788
789#if 0
790 uinteger_t tick = SIMICS_read_control_register(m_version, SIMICS_get_register_number(m_version, "tick"));
791 uinteger_t tick_cmpr = SIMICS_read_control_register(m_version, SIMICS_get_register_number(m_version, "tick_cmpr"));
792 uinteger_t stick = SIMICS_read_control_register(m_version, SIMICS_get_register_number(m_version, "stick"));
793 uinteger_t stick_cmpr = SIMICS_read_control_register(m_version, SIMICS_get_register_number(m_version, "stick_cmpr"));
794 cout << "START PROC " << m_version << hex << " tick = " << tick << " tick_cmpr = " << tick_cmpr << " stick = " << stick << " stick_cmpr = " << stick_cmpr << " cycle = "<< g_eventQueue_ptr->getTime() << dec << endl;;
795#endif
796
797 if (TSO && (request.getType() == CacheRequestType_LD || request.getType() == CacheRequestType_IFETCH)) {
798
799 // See if we can satisfy the load entirely from the store buffer
800 SubBlock subblock(line_address(request.getAddress()), request.getSize());
801 if (m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->trySubBlock(subblock)) {
802 DataBlock dummy;
803 hitCallback(request, dummy, GenericMachineType_NULL, thread); // Call with an 'empty' datablock, since the data is in the store buffer
804 return true;

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931void Sequencer::checkCoherence(const Address& addr) {
932#ifdef CHECK_COHERENCE
933 g_system_ptr->checkGlobalCoherenceInvariant(addr);
934#endif
935}
936
937bool Sequencer::getRubyMemoryValue(const Address& addr, char* value,
938 unsigned int size_in_bytes ) {
939 if(g_SIMICS){
940 for(unsigned int i=0; i < size_in_bytes; i++) {
941 value[i] = SIMICS_read_physical_memory( m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version,
942 addr.getAddress() + i, 1 );
943 }
944 return false; // Do nothing?
945 } else {
946 bool found = false;
947 const Address lineAddr = line_address(addr);
948 DataBlock data;
949 PhysAddress paddr(addr);
950 DataBlock* dataPtr = &data;

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1001 return true;
1002 }
1003}
1004
1005bool Sequencer::setRubyMemoryValue(const Address& addr, char *value,
1006 unsigned int size_in_bytes) {
1007 char test_buffer[64];
1008
1009 if(g_SIMICS){
1010 return false; // Do nothing?
1011 } else {
1012 // idea here is that coherent cache should find the
1013 // latest data, the update it
1014 bool found = false;
1015 const Address lineAddr = line_address(addr);
1016 PhysAddress paddr(addr);
1017 DataBlock data;

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1083 WARN_EXPR((int) test_buffer[0]);
1084 ERROR_MSG("setRubyMemoryValue failed to set value.");
1085 }
1086 }
1087
1088 return true;
1089 }
1090}