1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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312 }
313
314 markRemoved();
315}
316
317void
318Sequencer::invalidateSC(Addr address)
319{
320 AbstractCacheEntry *e = m_dataCache_ptr->lookup(address);
321 // The controller has lost the coherence permissions, hence the lock
322 // on the cache line maintained by the cache should be cleared.
323 if (e && e->isLocked(m_version)) {
324 e->clearLocked();
325 }
326}
327
328bool
329Sequencer::handleLlsc(Addr address, SequencerRequest* request)
330{
331 AbstractCacheEntry *e = m_dataCache_ptr->lookup(address);
332 if (!e)
333 return true;
334
335 // The success flag indicates whether the LLSC operation was successful.
336 // LL ops will always succeed, but SC may fail if the cache line is no
337 // longer locked.
338 bool success = true;
339 if (request->m_type == RubyRequestType_Store_Conditional) {
340 if (!e->isLocked(m_version)) {
341 //
342 // For failed SC requests, indicate the failure to the cpu by
343 // setting the extra data to zero.
344 //
345 request->pkt->req->setExtraData(0);
346 success = false;
347 } else {
348 //
349 // For successful SC requests, indicate the success to the cpu by
350 // setting the extra data to one.
351 //
352 request->pkt->req->setExtraData(1);
353 }
354 //
355 // Independent of success, all SC operations must clear the lock
356 //
357 e->clearLocked();
358 } else if (request->m_type == RubyRequestType_Load_Linked) {
359 //
360 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
361 // previously locked cache lines?
362 //
363 e->setLocked(m_version);
364 } else if (e->isLocked(m_version)) {
365 //
366 // Normal writes should clear the locked address
367 //
368 e->clearLocked();
369 }
370 return success;
371}
372
373void
374Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type,
375 const MachineType respondingMach,
376 bool isExternalHit, Cycles issuedTime,

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491void
492Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
493 bool llscSuccess,
494 const MachineType mach, const bool externalHit,
495 const Cycles initialRequestTime,
496 const Cycles forwardRequestTime,
497 const Cycles firstResponseTime)
498{
499 warn_once("Replacement policy updates recently became the responsibility "
500 "of SLICC state machines. Make sure to setMRU() near callbacks "
501 "in .sm files!");
502
503 PacketPtr pkt = srequest->pkt;
504 Addr request_address(pkt->getAddr());
505 RubyRequestType type = srequest->m_type;
506 Cycles issued_time = srequest->issue_time;
507
508 assert(curCycle() >= issued_time);
509 Cycles total_latency = curCycle() - issued_time;
510
511 // Profile the latency for all demand accesses.
512 recordMissLatency(total_latency, type, mach, externalHit, issued_time,
513 initialRequestTime, forwardRequestTime,
514 firstResponseTime, curCycle());
515

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