1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "base/str.hh"
30#include "cpu/rubytest/RubyTester.hh"
31#include "mem/protocol/CacheMsg.hh"
32#include "mem/protocol/Protocol.hh"
33#include "mem/protocol/Protocol.hh"
34#include "mem/ruby/buffers/MessageBuffer.hh"
35#include "mem/ruby/common/Global.hh"
36#include "mem/ruby/common/SubBlock.hh"
37#include "mem/ruby/libruby.hh"
38#include "mem/ruby/profiler/Profiler.hh"
39#include "mem/ruby/recorder/Tracer.hh"
40#include "mem/ruby/slicc_interface/AbstractController.hh"
41#include "mem/ruby/system/CacheMemory.hh"
42#include "mem/ruby/system/Sequencer.hh"
43#include "mem/ruby/system/System.hh"
44#include "mem/packet.hh"
45#include "params/RubySequencer.hh"
46
47using namespace std;
48
49Sequencer *
50RubySequencerParams::create()
51{
52 return new Sequencer(this);
53}
54
55Sequencer::Sequencer(const Params *p)
56 : RubyPort(p), deadlockCheckEvent(this)
57{
58 m_store_waiting_on_load_cycles = 0;
59 m_store_waiting_on_store_cycles = 0;
60 m_load_waiting_on_store_cycles = 0;
61 m_load_waiting_on_load_cycles = 0;
62
63 m_outstanding_count = 0;
64
65 m_max_outstanding_requests = 0;
66 m_deadlock_threshold = 0;
67 m_instCache_ptr = NULL;
68 m_dataCache_ptr = NULL;
69
70 m_instCache_ptr = p->icache;
71 m_dataCache_ptr = p->dcache;
72 m_max_outstanding_requests = p->max_outstanding_requests;
73 m_deadlock_threshold = p->deadlock_threshold;
74 m_usingRubyTester = p->using_ruby_tester;
75
76 assert(m_max_outstanding_requests > 0);
77 assert(m_deadlock_threshold > 0);
78 assert(m_instCache_ptr != NULL);
79 assert(m_dataCache_ptr != NULL);
80}
81
82Sequencer::~Sequencer()
83{
84}
85
86void
87Sequencer::wakeup()
88{
89 // Check for deadlock of any of the requests
90 Time current_time = g_eventQueue_ptr->getTime();
91
92 // Check across all outstanding requests
93 int total_outstanding = 0;
94
95 RequestTable::iterator read = m_readRequestTable.begin();
96 RequestTable::iterator read_end = m_readRequestTable.end();
97 for (; read != read_end; ++read) {
98 SequencerRequest* request = read->second;
99 if (current_time - request->issue_time < m_deadlock_threshold)
100 continue;
101
102 WARN_MSG("Possible Deadlock detected");
103 WARN_EXPR(m_version);
104 WARN_EXPR(request->ruby_request.paddr);
105 WARN_EXPR(m_readRequestTable.size());
106 WARN_EXPR(current_time);
107 WARN_EXPR(request->issue_time);
108 WARN_EXPR(current_time - request->issue_time);
109 ERROR_MSG("Aborting");
110 }
111
112 RequestTable::iterator write = m_writeRequestTable.begin();
113 RequestTable::iterator write_end = m_writeRequestTable.end();
114 for (; write != write_end; ++write) {
115 SequencerRequest* request = write->second;
116 if (current_time - request->issue_time < m_deadlock_threshold)
117 continue;
118
119 WARN_MSG("Possible Deadlock detected");
120 WARN_EXPR(m_version);
121 WARN_EXPR(request->ruby_request.paddr);
122 WARN_EXPR(current_time);
123 WARN_EXPR(request->issue_time);
124 WARN_EXPR(current_time - request->issue_time);
125 WARN_EXPR(m_writeRequestTable.size());
126 ERROR_MSG("Aborting");
127 }
128
129 total_outstanding += m_writeRequestTable.size();
130 total_outstanding += m_readRequestTable.size();
131
132 assert(m_outstanding_count == total_outstanding);
133
134 if (m_outstanding_count > 0) {
135 // If there are still outstanding requests, keep checking
136 schedule(deadlockCheckEvent,
137 m_deadlock_threshold * g_eventQueue_ptr->getClock() +
138 curTick);
139 }
140}
141
142void
143Sequencer::printStats(ostream & out) const
144{
145 out << "Sequencer: " << m_name << endl
146 << " store_waiting_on_load_cycles: "
147 << m_store_waiting_on_load_cycles << endl
148 << " store_waiting_on_store_cycles: "
149 << m_store_waiting_on_store_cycles << endl
150 << " load_waiting_on_load_cycles: "
151 << m_load_waiting_on_load_cycles << endl
152 << " load_waiting_on_store_cycles: "
153 << m_load_waiting_on_store_cycles << endl;
154}
155
156void
157Sequencer::printProgress(ostream& out) const
158{
159#if 0
160 int total_demand = 0;
161 out << "Sequencer Stats Version " << m_version << endl;
162 out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
163 out << "---------------" << endl;
164 out << "outstanding requests" << endl;
165
166 out << "proc " << m_Read
167 << " version Requests = " << m_readRequestTable.size() << endl;
168
169 // print the request table
170 RequestTable::iterator read = m_readRequestTable.begin();
171 RequestTable::iterator read_end = m_readRequestTable.end();
172 for (; read != read_end; ++read) {
173 SequencerRequest* request = read->second;
174 out << "\tRequest[ " << i << " ] = " << request->type
175 << " Address " << rkeys[i]
176 << " Posted " << request->issue_time
177 << " PF " << PrefetchBit_No << endl;
178 total_demand++;
179 }
180
181 out << "proc " << m_version
182 << " Write Requests = " << m_writeRequestTable.size << endl;
183
184 // print the request table
185 RequestTable::iterator write = m_writeRequestTable.begin();
186 RequestTable::iterator write_end = m_writeRequestTable.end();
187 for (; write != write_end; ++write) {
188 SequencerRequest* request = write->second;
189 out << "\tRequest[ " << i << " ] = " << request.getType()
190 << " Address " << wkeys[i]
191 << " Posted " << request.getTime()
192 << " PF " << request.getPrefetch() << endl;
193 if (request.getPrefetch() == PrefetchBit_No) {
194 total_demand++;
195 }
196 }
197
198 out << endl;
199
200 out << "Total Number Outstanding: " << m_outstanding_count << endl
201 << "Total Number Demand : " << total_demand << endl
202 << "Total Number Prefetches : " << m_outstanding_count - total_demand
203 << endl << endl << endl;
204#endif
205}
206
207void
208Sequencer::printConfig(ostream& out) const
209{
210 out << "Seqeuncer config: " << m_name << endl
211 << " controller: " << m_controller->getName() << endl
212 << " version: " << m_version << endl
213 << " max_outstanding_requests: " << m_max_outstanding_requests << endl
214 << " deadlock_threshold: " << m_deadlock_threshold << endl;
215}
216
217// Insert the request on the correct request table. Return true if
218// the entry was already present.
219bool
220Sequencer::insertRequest(SequencerRequest* request)
221{
222 int total_outstanding =
223 m_writeRequestTable.size() + m_readRequestTable.size();
224
225 assert(m_outstanding_count == total_outstanding);
226
227 // See if we should schedule a deadlock check
228 if (deadlockCheckEvent.scheduled() == false) {
229 schedule(deadlockCheckEvent, m_deadlock_threshold + curTick);
230 }
231
232 Address line_addr(request->ruby_request.paddr);
233 line_addr.makeLineAddress();
234 if ((request->ruby_request.type == RubyRequestType_ST) ||
235 (request->ruby_request.type == RubyRequestType_RMW_Read) ||
236 (request->ruby_request.type == RubyRequestType_RMW_Write) ||
237 (request->ruby_request.type == RubyRequestType_Locked_Read) ||
238 (request->ruby_request.type == RubyRequestType_Locked_Write)) {
239 pair<RequestTable::iterator, bool> r =
240 m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0));
241 bool success = r.second;
242 RequestTable::iterator i = r.first;
243 if (!success) {
244 i->second = request;
245 // return true;
246
247 // drh5: isn't this an error? do you lose the initial request?
248 assert(0);
249 }
250 i->second = request;
251 m_outstanding_count++;
252 } else {
253 pair<RequestTable::iterator, bool> r =
254 m_readRequestTable.insert(RequestTable::value_type(line_addr, 0));
255 bool success = r.second;
256 RequestTable::iterator i = r.first;
257 if (!success) {
258 i->second = request;
259 // return true;
260
261 // drh5: isn't this an error? do you lose the initial request?
262 assert(0);
263 }
264 i->second = request;
265 m_outstanding_count++;
266 }
267
268 g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
269
270 total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
271 assert(m_outstanding_count == total_outstanding);
272
273 return false;
274}
275
276void
277Sequencer::markRemoved()
278{
279 m_outstanding_count--;
280 assert(m_outstanding_count ==
281 m_writeRequestTable.size() + m_readRequestTable.size());
282}
283
284void
285Sequencer::removeRequest(SequencerRequest* srequest)
286{
287 assert(m_outstanding_count ==
288 m_writeRequestTable.size() + m_readRequestTable.size());
289
290 const RubyRequest & ruby_request = srequest->ruby_request;
291 Address line_addr(ruby_request.paddr);
292 line_addr.makeLineAddress();
293 if ((ruby_request.type == RubyRequestType_ST) ||
294 (ruby_request.type == RubyRequestType_RMW_Read) ||
295 (ruby_request.type == RubyRequestType_RMW_Write) ||
296 (ruby_request.type == RubyRequestType_Locked_Read) ||
297 (ruby_request.type == RubyRequestType_Locked_Write)) {
298 m_writeRequestTable.erase(line_addr);
299 } else {
300 m_readRequestTable.erase(line_addr);
301 }
302
303 markRemoved();
304}
305
306void
307Sequencer::handleLlscWrites(const Address& address, SequencerRequest* request)
308{
309 if (request->ruby_request.type == RubyRequestType_Locked_Write) {
310 if (!m_dataCache_ptr->isLocked(address, m_version)) {
311 //
312 // For failed SC requests, indicate the failure to the cpu by
313 // setting the extra data to zero.
314 //
315 request->ruby_request.pkt->req->setExtraData(0);
316 } else {
317 //
318 // For successful SC requests, indicate the success to the cpu by
319 // setting the extra data to one.
320 //
321 request->ruby_request.pkt->req->setExtraData(1);
322 }
323 m_dataCache_ptr->clearLocked(address);
324 } else if (request->ruby_request.type == RubyRequestType_Locked_Read) {
325 //
326 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
327 // previously locked cache lines?
328 //
329 m_dataCache_ptr->setLocked(address, m_version);
330 } else if (m_dataCache_ptr->isLocked(address, m_version)) {
331 //
332 // Normal writes should clear the locked address
333 //
334 m_dataCache_ptr->clearLocked(address);
335 }
336}
337
338void
339Sequencer::writeCallback(const Address& address, DataBlock& data)
340{
341 writeCallback(address, GenericMachineType_NULL, data);
342}
343
344void
345Sequencer::writeCallback(const Address& address,
346 GenericMachineType mach,
347 DataBlock& data)
348{
349 assert(address == line_address(address));
350 assert(m_writeRequestTable.count(line_address(address)));
351
352 RequestTable::iterator i = m_writeRequestTable.find(address);
353 assert(i != m_writeRequestTable.end());
354 SequencerRequest* request = i->second;
355
356 m_writeRequestTable.erase(i);
357 markRemoved();
358
359 assert((request->ruby_request.type == RubyRequestType_ST) ||
360 (request->ruby_request.type == RubyRequestType_RMW_Read) ||
361 (request->ruby_request.type == RubyRequestType_RMW_Write) ||
362 (request->ruby_request.type == RubyRequestType_Locked_Read) ||
363 (request->ruby_request.type == RubyRequestType_Locked_Write));
364
365 //
366 // For Alpha, properly handle LL, SC, and write requests with respect to
367 // locked cache blocks.
368 //
369 handleLlscWrites(address, request);
370
371 if (request->ruby_request.type == RubyRequestType_RMW_Read) {
372 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
373 } else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
374 m_controller->unblock(address);
375 }
376
377 hitCallback(request, mach, data);
378}
379
380void
381Sequencer::readCallback(const Address& address, DataBlock& data)
382{
383 readCallback(address, GenericMachineType_NULL, data);
384}
385
386void
387Sequencer::readCallback(const Address& address,
388 GenericMachineType mach,
389 DataBlock& data)
390{
391 assert(address == line_address(address));
392 assert(m_readRequestTable.count(line_address(address)));
393
394 RequestTable::iterator i = m_readRequestTable.find(address);
395 assert(i != m_readRequestTable.end());
396 SequencerRequest* request = i->second;
397
398 m_readRequestTable.erase(i);
399 markRemoved();
400
401 assert((request->ruby_request.type == RubyRequestType_LD) ||
402 (request->ruby_request.type == RubyRequestType_RMW_Read) ||
403 (request->ruby_request.type == RubyRequestType_IFETCH));
404
405 hitCallback(request, mach, data);
406}
407
408void
409Sequencer::hitCallback(SequencerRequest* srequest,
410 GenericMachineType mach,
411 DataBlock& data)
412{
413 const RubyRequest & ruby_request = srequest->ruby_request;
414 Address request_address(ruby_request.paddr);
415 Address request_line_address(ruby_request.paddr);
416 request_line_address.makeLineAddress();
417 RubyRequestType type = ruby_request.type;
418 Time issued_time = srequest->issue_time;
419
420 // Set this cache entry to the most recently used
421 if (type == RubyRequestType_IFETCH) {
422 if (m_instCache_ptr->isTagPresent(request_line_address))
423 m_instCache_ptr->setMRU(request_line_address);
424 } else {
425 if (m_dataCache_ptr->isTagPresent(request_line_address))
426 m_dataCache_ptr->setMRU(request_line_address);
427 }
428
429 assert(g_eventQueue_ptr->getTime() >= issued_time);
430 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
431
432 // Profile the miss latency for all non-zero demand misses
433 if (miss_latency != 0) {
434 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
435
436 if (Debug::getProtocolTrace()) {
437 g_system_ptr->getProfiler()->
438 profileTransition("Seq", m_version,
439 Address(ruby_request.paddr), "", "Done", "",
440 csprintf("%d cycles", miss_latency));
441 }
442 }
443#if 0
444 if (request.getPrefetch() == PrefetchBit_Yes) {
445 return; // Ignore the prefetch
446 }
447#endif
448
449 // update the data
450 if (ruby_request.data != NULL) {
451 if ((type == RubyRequestType_LD) ||
452 (type == RubyRequestType_IFETCH) ||
453 (type == RubyRequestType_RMW_Read) ||
454 (type == RubyRequestType_Locked_Read)) {
455
456 memcpy(ruby_request.data,
457 data.getData(request_address.getOffset(), ruby_request.len),
458 ruby_request.len);
459 } else {
460 data.setData(ruby_request.data, request_address.getOffset(),
461 ruby_request.len);
462 }
463 } else {
464 DPRINTF(MemoryAccess,
465 "WARNING. Data not transfered from Ruby to M5 for type %s\n",
466 RubyRequestType_to_string(type));
467 }
468
469 // If using the RubyTester, update the RubyTester sender state's
470 // subBlock with the recieved data. The tester will later access
471 // this state.
472 // Note: RubyPort will access it's sender state before the
473 // RubyTester.
474 if (m_usingRubyTester) {
475 RubyPort::SenderState *requestSenderState =
476 safe_cast<RubyPort::SenderState*>(ruby_request.pkt->senderState);
477 RubyTester::SenderState* testerSenderState =
478 safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
479 testerSenderState->subBlock->mergeFrom(data);
480 }
481
482 ruby_hit_callback(ruby_request.pkt);
483 delete srequest;
484}
485
486// Returns true if the sequencer already has a load or store outstanding
487RequestStatus
488Sequencer::getRequestStatus(const RubyRequest& request)
489{
490 bool is_outstanding_store =
491 !!m_writeRequestTable.count(line_address(Address(request.paddr)));
492 bool is_outstanding_load =
493 !!m_readRequestTable.count(line_address(Address(request.paddr)));
494 if (is_outstanding_store) {
495 if ((request.type == RubyRequestType_LD) ||
496 (request.type == RubyRequestType_IFETCH) ||
497 (request.type == RubyRequestType_RMW_Read)) {
498 m_store_waiting_on_load_cycles++;
499 } else {
500 m_store_waiting_on_store_cycles++;
501 }
502 return RequestStatus_Aliased;
503 } else if (is_outstanding_load) {
504 if ((request.type == RubyRequestType_ST) ||
505 (request.type == RubyRequestType_RMW_Write)) {
506 m_load_waiting_on_store_cycles++;
507 } else {
508 m_load_waiting_on_load_cycles++;
509 }
510 return RequestStatus_Aliased;
511 }
512
513 if (m_outstanding_count >= m_max_outstanding_requests) {
514 return RequestStatus_BufferFull;
515 }
516
517 return RequestStatus_Ready;
518}
519
520bool
521Sequencer::empty() const
522{
523 return m_writeRequestTable.empty() && m_readRequestTable.empty();
524}
525
526RequestStatus
527Sequencer::makeRequest(const RubyRequest &request)
528{
529 assert(Address(request.paddr).getOffset() + request.len <=
530 RubySystem::getBlockSizeBytes());
531 RequestStatus status = getRequestStatus(request);
532 if (status != RequestStatus_Ready)
533 return status;
534
535 SequencerRequest *srequest =
536 new SequencerRequest(request, g_eventQueue_ptr->getTime());
537 bool found = insertRequest(srequest);
538 if (found) {
539 panic("Sequencer::makeRequest should never be called if the "
540 "request is already outstanding\n");
541 return RequestStatus_NULL;
542 }
543
544 issueRequest(request);
545
546 // TODO: issue hardware prefetches here
547 return RequestStatus_Issued;
548}
549
550void
551Sequencer::issueRequest(const RubyRequest& request)
552{
553 // TODO: get rid of CacheMsg, CacheRequestType, and
554 // AccessModeTYpe, & have SLICC use RubyRequest and subtypes
555 // natively
556 CacheRequestType ctype;
557 switch(request.type) {
558 case RubyRequestType_IFETCH:
559 ctype = CacheRequestType_IFETCH;
560 break;
561 case RubyRequestType_LD:
562 ctype = CacheRequestType_LD;
563 break;
564 case RubyRequestType_ST:
565 ctype = CacheRequestType_ST;
566 break;
567 case RubyRequestType_Locked_Read:
568 case RubyRequestType_Locked_Write:
569 ctype = CacheRequestType_ATOMIC;
570 break;
571 case RubyRequestType_RMW_Read:
572 ctype = CacheRequestType_ATOMIC;
573 break;
574 case RubyRequestType_RMW_Write:
575 ctype = CacheRequestType_ATOMIC;
576 break;
577 default:
578 assert(0);
579 }
580
581 AccessModeType amtype;
582 switch(request.access_mode){
583 case RubyAccessMode_User:
584 amtype = AccessModeType_UserMode;
585 break;
586 case RubyAccessMode_Supervisor:
587 amtype = AccessModeType_SupervisorMode;
588 break;
589 case RubyAccessMode_Device:
590 amtype = AccessModeType_UserMode;
591 break;
592 default:
593 assert(0);
594 }
595
596 Address line_addr(request.paddr);
597 line_addr.makeLineAddress();
598 CacheMsg *msg = new CacheMsg(line_addr, Address(request.paddr), ctype,
599 Address(request.pc), amtype, request.len, PrefetchBit_No,
600 request.proc_id);
601
602 if (Debug::getProtocolTrace()) {
603 g_system_ptr->getProfiler()->
604 profileTransition("Seq", m_version, Address(request.paddr),
605 "", "Begin", "",
606 RubyRequestType_to_string(request.type));
607 }
608
609 if (g_system_ptr->getTracer()->traceEnabled()) {
610 g_system_ptr->getTracer()->
611 traceRequest(this, line_addr, Address(request.pc),
612 request.type, g_eventQueue_ptr->getTime());
613 }
614
615 Time latency = 0; // initialzed to an null value
616
617 if (request.type == RubyRequestType_IFETCH)
618 latency = m_instCache_ptr->getLatency();
619 else
620 latency = m_dataCache_ptr->getLatency();
621
622 // Send the message to the cache controller
623 assert(latency > 0);
624
625 assert(m_mandatory_q_ptr != NULL);
626 m_mandatory_q_ptr->enqueue(msg, latency);
627}
628
629#if 0
630bool
631Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
632 AccessModeType access_mode,
633 int size, DataBlock*& data_ptr)
634{
635 CacheMemory *cache =
636 (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
637
638 return cache->tryCacheAccess(line_address(addr), type, data_ptr);
639}
640#endif
641
642template <class KEY, class VALUE>
643std::ostream &
644operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
645{
646 typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
647 typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
648
649 out << "[";
650 for (; i != end; ++i)
651 out << " " << i->first << "=" << i->second;
652 out << " ]";
653
654 return out;
655}
656
657void
658Sequencer::print(ostream& out) const
659{
660 out << "[Sequencer: " << m_version
661 << ", outstanding requests: " << m_outstanding_count
662 << ", read request table: " << m_readRequestTable
663 << ", write request table: " << m_writeRequestTable
664 << "]";
665}
666
667// this can be called from setState whenever coherence permissions are
668// upgraded when invoked, coherence violations will be checked for the
669// given block
670void
671Sequencer::checkCoherence(const Address& addr)
672{
673#ifdef CHECK_COHERENCE
674 g_system_ptr->checkGlobalCoherenceInvariant(addr);
675#endif
676}