1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "mem/ruby/common/SubBlock.hh"
37#include "mem/ruby/libruby.hh"
38#include "mem/ruby/profiler/Profiler.hh"
39#include "mem/ruby/recorder/Tracer.hh"
40#include "mem/ruby/slicc_interface/AbstractController.hh"
41#include "mem/ruby/system/CacheMemory.hh"
42#include "mem/ruby/system/Sequencer.hh"
43#include "mem/ruby/system/System.hh"
44#include "mem/packet.hh"
45#include "params/RubySequencer.hh"
46
47using namespace std;
48
49Sequencer *
50RubySequencerParams::create()
51{
52 return new Sequencer(this);

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299 } else {
300 m_readRequestTable.erase(line_addr);
301 }
302
303 markRemoved();
304}
305
306void
307Sequencer::handleLlscWrites(const Address& address, SequencerRequest* request)
308{
309 if (request->ruby_request.type == RubyRequestType_Locked_Write) {
310 if (!m_dataCache_ptr->isLocked(address, m_version)) {
311 //
312 // For failed SC requests, indicate the failure to the cpu by
313 // setting the extra data to zero.
314 //
315 request->ruby_request.pkt->req->setExtraData(0);
316 } else {
317 //
318 // For successful SC requests, indicate the success to the cpu by
319 // setting the extra data to one.
320 //
321 request->ruby_request.pkt->req->setExtraData(1);
322 }
323 m_dataCache_ptr->clearLocked(address);
324 } else if (request->ruby_request.type == RubyRequestType_Locked_Read) {
325 //
326 // Note: To fully follow Alpha LLSC semantics, should the LL clear any
327 // previously locked cache lines?
328 //
329 m_dataCache_ptr->setLocked(address, m_version);
330 } else if (m_dataCache_ptr->isLocked(address, m_version)) {
331 //
332 // Normal writes should clear the locked address
333 //
334 m_dataCache_ptr->clearLocked(address);
335 }
336}
337
338void
339Sequencer::writeCallback(const Address& address, DataBlock& data)
340{
341 writeCallback(address, GenericMachineType_NULL, data);
342}
343
344void
345Sequencer::writeCallback(const Address& address,
346 GenericMachineType mach,

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357 markRemoved();
358
359 assert((request->ruby_request.type == RubyRequestType_ST) ||
360 (request->ruby_request.type == RubyRequestType_RMW_Read) ||
361 (request->ruby_request.type == RubyRequestType_RMW_Write) ||
362 (request->ruby_request.type == RubyRequestType_Locked_Read) ||
363 (request->ruby_request.type == RubyRequestType_Locked_Write));
364
365 //
366 // For Alpha, properly handle LL, SC, and write requests with respect to
367 // locked cache blocks.
368 //
369 handleLlscWrites(address, request);
370
371 if (request->ruby_request.type == RubyRequestType_RMW_Read) {
372 m_controller->blockOnQueue(address, m_mandatory_q_ptr);
373 } else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
374 m_controller->unblock(address);
375 }
376
377 hitCallback(request, mach, data);
378}
379

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536 new SequencerRequest(request, g_eventQueue_ptr->getTime());
537 bool found = insertRequest(srequest);
538 if (found) {
539 panic("Sequencer::makeRequest should never be called if the "
540 "request is already outstanding\n");
541 return RequestStatus_NULL;
542 }
543
544 issueRequest(request);
545
546 // TODO: issue hardware prefetches here
547 return RequestStatus_Issued;
548}
549
550void
551Sequencer::issueRequest(const RubyRequest& request)

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