1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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55Sequencer::Sequencer(const Params *p)
56 : RubyPort(p), m_IncompleteTimes(MachineType_NUM),
57 deadlockCheckEvent([this]{ wakeup(); }, "Sequencer deadlock check")
58{
59 m_outstanding_count = 0;
60
61 m_instCache_ptr = p->icache;
62 m_dataCache_ptr = p->dcache;
63 m_max_outstanding_requests = p->max_outstanding_requests;
64 m_deadlock_threshold = p->deadlock_threshold;
65
66 m_coreId = p->coreid; // for tracking the two CorePair sequencers
67 assert(m_max_outstanding_requests > 0);
68 assert(m_deadlock_threshold > 0);
69 assert(m_instCache_ptr != NULL);
70 assert(m_dataCache_ptr != NULL);
71
72 m_runningGarnetStandalone = p->garnet_standalone;
73}
74
75Sequencer::~Sequencer()
76{
77}
78

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641 RubyAccessMode_Supervisor, pkt,
642 PrefetchBit_No, proc_id, core_id);
643
644 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
645 curTick(), m_version, "Seq", "Begin", "", "",
646 printAddress(msg->getPhysicalAddress()),
647 RubyRequestType_to_string(secondary_type));
648
649 Tick latency = cyclesToTicks(
650 m_controller->mandatoryQueueLatency(secondary_type));
651 assert(latency > 0);
652
653 assert(m_mandatory_q_ptr != NULL);
654 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
655}
656
657template <class KEY, class VALUE>
658std::ostream &
659operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map)
660{
661 auto i = map.begin();
662 auto end = map.end();

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