1/* 2 * Copyright (c) 2013-2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 129 unchanged lines hidden (view full) --- 138 m_max_outstanding_requests = p->max_outstanding_requests; 139 m_deadlock_threshold = p->deadlock_threshold; 140 141 assert(m_max_outstanding_requests > 0); 142 assert(m_deadlock_threshold > 0); 143 assert(m_instCache_ptr); 144 assert(m_dataCache_ptr); 145 |
146 m_runningGarnetStandalone = p->garnet_standalone; 147 assumingRfOCoherence = p->assume_rfo; 148} 149 150GPUCoalescer::~GPUCoalescer() 151{ 152} 153 --- 789 unchanged lines hidden (view full) --- 943 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n", 944 curTick(), m_version, "Coal", "Begin", "", "", 945 printAddress(msg->getPhysicalAddress()), 946 RubyRequestType_to_string(secondary_type)); 947 948 fatal_if(secondary_type == RubyRequestType_IFETCH, 949 "there should not be any I-Fetch requests in the GPU Coalescer"); 950 |
951 Tick latency = cyclesToTicks( 952 m_controller->mandatoryQueueLatency(secondary_type)); 953 assert(latency > 0); |
954 955 assert(m_mandatory_q_ptr); |
956 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency); |
957} 958 959template <class KEY, class VALUE> 960std::ostream & 961operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map) 962{ 963 out << "["; 964 for (auto i = map.begin(); i != map.end(); ++i) --- 411 unchanged lines hidden --- |