DMASequencer.hh (8615:e66a566f2cfa) DMASequencer.hh (8688:5ca9dd977386)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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50{
51 public:
52 typedef DMASequencerParams Params;
53 DMASequencer(const Params *);
54 void init();
55 /* external interface */
56 RequestStatus makeRequest(PacketPtr pkt);
57 bool busy() { return m_is_busy;}
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 41 unchanged lines hidden (view full) ---

50{
51 public:
52 typedef DMASequencerParams Params;
53 DMASequencer(const Params *);
54 void init();
55 /* external interface */
56 RequestStatus makeRequest(PacketPtr pkt);
57 bool busy() { return m_is_busy;}
58 int outstandingCount() const { return (m_is_busy ? 1 : 0); }
59 bool isDeadlockEventScheduled() const { return false; }
60 void descheduleDeadlockEvent() {}
58
59 /* SLICC callback */
60 void dataCallback(const DataBlock & dblk);
61 void ackCallback();
62
63 void printConfig(std::ostream & out);
64
65 private:
66 void issueNext();
67
68 private:
69 bool m_is_busy;
70 uint64_t m_data_block_mask;
71 DMARequest active_request;
72 int num_active_requests;
73};
74
75#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
61
62 /* SLICC callback */
63 void dataCallback(const DataBlock & dblk);
64 void ackCallback();
65
66 void printConfig(std::ostream & out);
67
68 private:
69 void issueNext();
70
71 private:
72 bool m_is_busy;
73 uint64_t m_data_block_mask;
74 DMARequest active_request;
75 int num_active_requests;
76};
77
78#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__