DMASequencer.hh (7008:90c097fb76e1) | DMASequencer.hh (7039:bc0b6ea676b5) |
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1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 12 unchanged lines hidden (view full) --- 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 | 1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 12 unchanged lines hidden (view full) --- 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 |
29#ifndef DMASEQUENCER_H 30#define DMASEQUENCER_H | 29#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 30#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ |
31 32#include <ostream> | 31 32#include <ostream> |
33 |
|
33#include "mem/ruby/common/DataBlock.hh" 34#include "mem/ruby/system/RubyPort.hh" | 34#include "mem/ruby/common/DataBlock.hh" 35#include "mem/ruby/system/RubyPort.hh" |
35 | |
36#include "params/DMASequencer.hh" 37 | 36#include "params/DMASequencer.hh" 37 |
38struct DMARequest { 39 uint64_t start_paddr; 40 int len; 41 bool write; 42 int bytes_completed; 43 int bytes_issued; 44 uint8* data; 45 PacketPtr pkt; | 38struct DMARequest 39{ 40 uint64_t start_paddr; 41 int len; 42 bool write; 43 int bytes_completed; 44 int bytes_issued; 45 uint8* data; 46 PacketPtr pkt; |
46}; 47 | 47}; 48 |
48class DMASequencer :public RubyPort { 49public: | 49class DMASequencer : public RubyPort 50{ 51 public: |
50 typedef DMASequencerParams Params; | 52 typedef DMASequencerParams Params; |
51 DMASequencer(const Params *); 52 void init(); 53 /* external interface */ 54 RequestStatus makeRequest(const RubyRequest & request); 55 bool busy() { return m_is_busy;} | 53 DMASequencer(const Params *); 54 void init(); 55 /* external interface */ 56 RequestStatus makeRequest(const RubyRequest & request); 57 bool busy() { return m_is_busy;} |
56 | 58 |
57 /* SLICC callback */ 58 void dataCallback(const DataBlock & dblk); 59 void ackCallback(); | 59 /* SLICC callback */ 60 void dataCallback(const DataBlock & dblk); 61 void ackCallback(); |
60 | 62 |
61 void printConfig(std::ostream & out); | 63 void printConfig(std::ostream & out); |
62 | 64 |
63private: 64 void issueNext(); | 65 private: 66 void issueNext(); |
65 | 67 |
66private: 67 bool m_is_busy; 68 uint64_t m_data_block_mask; 69 DMARequest active_request; 70 int num_active_requests; | 68 private: 69 bool m_is_busy; 70 uint64_t m_data_block_mask; 71 DMARequest active_request; 72 int num_active_requests; |
71}; 72 | 73}; 74 |
73#endif // DMACONTROLLER_H | 75#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ |