DMASequencer.hh (11169:44b5c183c3cd) | DMASequencer.hh (11339:c45bfadcd51b) |
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1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 */ 28 29#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 30#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 31 32#include <memory> 33#include <ostream> 34 | 1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 */ 28 29#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 30#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 31 32#include <memory> 33#include <ostream> 34 |
35#include "mem/mem_object.hh" | |
36#include "mem/protocol/DMASequencerRequestType.hh" | 35#include "mem/protocol/DMASequencerRequestType.hh" |
37#include "mem/protocol/RequestStatus.hh" | |
38#include "mem/ruby/common/DataBlock.hh" | 36#include "mem/ruby/common/DataBlock.hh" |
39#include "mem/ruby/network/MessageBuffer.hh" 40#include "mem/ruby/system/RubySystem.hh" 41#include "mem/simple_mem.hh" 42#include "mem/tport.hh" | 37#include "mem/ruby/system/RubyPort.hh" |
43#include "params/DMASequencer.hh" 44 | 38#include "params/DMASequencer.hh" 39 |
45class AbstractController; 46 | |
47struct DMARequest 48{ 49 uint64_t start_paddr; 50 int len; 51 bool write; 52 int bytes_completed; 53 int bytes_issued; 54 uint8_t *data; 55 PacketPtr pkt; 56}; 57 | 40struct DMARequest 41{ 42 uint64_t start_paddr; 43 int len; 44 bool write; 45 int bytes_completed; 46 int bytes_issued; 47 uint8_t *data; 48 PacketPtr pkt; 49}; 50 |
58class DMASequencer : public MemObject | 51class DMASequencer : public RubyPort |
59{ 60 public: 61 typedef DMASequencerParams Params; 62 DMASequencer(const Params *); 63 void init() override; | 52{ 53 public: 54 typedef DMASequencerParams Params; 55 DMASequencer(const Params *); 56 void init() override; |
64 RubySystem *m_ruby_system; | |
65 | 57 |
66 public: 67 class MemSlavePort : public QueuedSlavePort 68 { 69 private: 70 RespPacketQueue queue; 71 RubySystem* m_ruby_system; 72 bool access_backing_store; 73 74 public: 75 MemSlavePort(const std::string &_name, DMASequencer *_port, 76 PortID id, RubySystem *_ruby_system, 77 bool _access_backing_store); 78 void hitCallback(PacketPtr pkt); 79 void evictionCallback(Addr address); 80 81 protected: 82 bool recvTimingReq(PacketPtr pkt); 83 84 Tick recvAtomic(PacketPtr pkt) 85 { panic("DMASequencer::MemSlavePort::recvAtomic() not implemented!\n"); } 86 87 void recvFunctional(PacketPtr pkt) 88 { panic("DMASequencer::MemSlavePort::recvFunctional() not implemented!\n"); } 89 90 AddrRangeList getAddrRanges() const 91 { AddrRangeList ranges; return ranges; } 92 93 private: 94 bool isPhysMemAddress(Addr addr) const; 95 }; 96 97 BaseSlavePort &getSlavePort(const std::string &if_name, 98 PortID idx = InvalidPortID) override; 99 | |
100 /* external interface */ 101 RequestStatus makeRequest(PacketPtr pkt); 102 bool busy() { return m_is_busy;} 103 int outstandingCount() const { return (m_is_busy ? 1 : 0); } 104 bool isDeadlockEventScheduled() const { return false; } 105 void descheduleDeadlockEvent() {} 106 | 58 /* external interface */ 59 RequestStatus makeRequest(PacketPtr pkt); 60 bool busy() { return m_is_busy;} 61 int outstandingCount() const { return (m_is_busy ? 1 : 0); } 62 bool isDeadlockEventScheduled() const { return false; } 63 void descheduleDeadlockEvent() {} 64 |
107 // Called by the controller to give the sequencer a pointer. 108 // A pointer to the controller is needed for atomic support. 109 void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 110 uint32_t getId() { return m_version; } 111 DrainState drain() override; 112 | |
113 /* SLICC callback */ 114 void dataCallback(const DataBlock & dblk); 115 void ackCallback(); 116 117 void recordRequestType(DMASequencerRequestType requestType); 118 119 private: 120 void issueNext(); | 65 /* SLICC callback */ 66 void dataCallback(const DataBlock & dblk); 67 void ackCallback(); 68 69 void recordRequestType(DMASequencerRequestType requestType); 70 71 private: 72 void issueNext(); |
121 void ruby_hit_callback(PacketPtr pkt); 122 void testDrainComplete(); | |
123 | 73 |
124 /** 125 * Called by the PIO port when receiving a timing response. 126 * 127 * @param pkt Response packet 128 * @param master_port_id Port id of the PIO port 129 * 130 * @return Whether successfully sent 131 */ 132 bool recvTimingResp(PacketPtr pkt, PortID master_port_id); 133 unsigned int getChildDrainCount(); 134 135 private: 136 uint32_t m_version; 137 AbstractController* m_controller; 138 MessageBuffer* m_mandatory_q_ptr; 139 bool m_usingRubyTester; 140 141 MemSlavePort slave_port; 142 143 System* system; 144 145 bool retry; | |
146 bool m_is_busy; 147 uint64_t m_data_block_mask; 148 DMARequest active_request; 149}; 150 151#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ | 74 bool m_is_busy; 75 uint64_t m_data_block_mask; 76 DMARequest active_request; 77}; 78 79#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ |