DMASequencer.hh (10472:399f35ed5cca) | DMASequencer.hh (10518:30e3715c9405) |
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1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 29#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 30#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 31 32#include <ostream> 33#include <memory> 34 35#include "mem/protocol/DMASequencerRequestType.hh" | 1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 29#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 30#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 31 32#include <ostream> 33#include <memory> 34 35#include "mem/protocol/DMASequencerRequestType.hh" |
36#include "mem/protocol/RequestStatus.hh" |
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36#include "mem/ruby/common/DataBlock.hh" | 37#include "mem/ruby/common/DataBlock.hh" |
37#include "mem/ruby/system/RubyPort.hh" | 38#include "mem/ruby/network/MessageBuffer.hh" 39#include "mem/ruby/system/System.hh" 40#include "mem/mem_object.hh" 41#include "mem/tport.hh" |
38#include "params/DMASequencer.hh" 39 | 42#include "params/DMASequencer.hh" 43 |
44class AbstractController; 45 |
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40struct DMARequest 41{ 42 uint64_t start_paddr; 43 int len; 44 bool write; 45 int bytes_completed; 46 int bytes_issued; 47 uint8_t *data; 48 PacketPtr pkt; 49}; 50 | 46struct DMARequest 47{ 48 uint64_t start_paddr; 49 int len; 50 bool write; 51 int bytes_completed; 52 int bytes_issued; 53 uint8_t *data; 54 PacketPtr pkt; 55}; 56 |
51class DMASequencer : public RubyPort | 57class DMASequencer : public MemObject |
52{ 53 public: 54 typedef DMASequencerParams Params; 55 DMASequencer(const Params *); 56 void init(); | 58{ 59 public: 60 typedef DMASequencerParams Params; 61 DMASequencer(const Params *); 62 void init(); |
63 64 public: 65 class MemSlavePort : public QueuedSlavePort 66 { 67 private: 68 SlavePacketQueue queue; 69 bool access_phys_mem; 70 71 public: 72 MemSlavePort(const std::string &_name, DMASequencer *_port, 73 bool _access_phys_mem, PortID id); 74 void hitCallback(PacketPtr pkt); 75 void evictionCallback(const Address& address); 76 77 protected: 78 bool recvTimingReq(PacketPtr pkt); 79 80 Tick recvAtomic(PacketPtr pkt) 81 { panic("DMASequencer::MemSlavePort::recvAtomic() not implemented!\n"); } 82 83 void recvFunctional(PacketPtr pkt) 84 { panic("DMASequencer::MemSlavePort::recvFunctional() not implemented!\n"); } 85 86 AddrRangeList getAddrRanges() const 87 { AddrRangeList ranges; return ranges; } 88 89 private: 90 bool isPhysMemAddress(Addr addr) const; 91 }; 92 93 BaseSlavePort &getSlavePort(const std::string &if_name, 94 PortID idx = InvalidPortID); 95 |
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57 /* external interface */ 58 RequestStatus makeRequest(PacketPtr pkt); 59 bool busy() { return m_is_busy;} 60 int outstandingCount() const { return (m_is_busy ? 1 : 0); } 61 bool isDeadlockEventScheduled() const { return false; } 62 void descheduleDeadlockEvent() {} 63 | 96 /* external interface */ 97 RequestStatus makeRequest(PacketPtr pkt); 98 bool busy() { return m_is_busy;} 99 int outstandingCount() const { return (m_is_busy ? 1 : 0); } 100 bool isDeadlockEventScheduled() const { return false; } 101 void descheduleDeadlockEvent() {} 102 |
103 // Called by the controller to give the sequencer a pointer. 104 // A pointer to the controller is needed for atomic support. 105 void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 106 uint32_t getId() { return m_version; } 107 unsigned int drain(DrainManager *dm); 108 |
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64 /* SLICC callback */ 65 void dataCallback(const DataBlock & dblk); 66 void ackCallback(); 67 68 void recordRequestType(DMASequencerRequestType requestType); 69 70 private: 71 void issueNext(); | 109 /* SLICC callback */ 110 void dataCallback(const DataBlock & dblk); 111 void ackCallback(); 112 113 void recordRequestType(DMASequencerRequestType requestType); 114 115 private: 116 void issueNext(); |
117 void ruby_hit_callback(PacketPtr pkt); 118 void testDrainComplete(); |
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72 | 119 |
120 /** 121 * Called by the PIO port when receiving a timing response. 122 * 123 * @param pkt Response packet 124 * @param master_port_id Port id of the PIO port 125 * 126 * @return Whether successfully sent 127 */ 128 bool recvTimingResp(PacketPtr pkt, PortID master_port_id); 129 unsigned int getChildDrainCount(DrainManager *dm); 130 |
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73 private: | 131 private: |
132 uint32_t m_version; 133 AbstractController* m_controller; 134 MessageBuffer* m_mandatory_q_ptr; 135 bool m_usingRubyTester; 136 137 MemSlavePort slave_port; 138 139 DrainManager *drainManager; 140 System* system; 141 142 bool retry; 143 bool access_phys_mem; 144 |
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74 bool m_is_busy; 75 uint64_t m_data_block_mask; 76 DMARequest active_request; 77}; 78 79#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ | 145 bool m_is_busy; 146 uint64_t m_data_block_mask; 147 DMARequest active_request; 148}; 149 150#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ |