1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 30#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__ 31 32#include <ostream> 33#include <memory> 34 35#include "mem/protocol/DMASequencerRequestType.hh" 36#include "mem/protocol/RequestStatus.hh" 37#include "mem/ruby/common/DataBlock.hh" 38#include "mem/ruby/network/MessageBuffer.hh" 39#include "mem/ruby/system/System.hh" 40#include "mem/mem_object.hh" 41#include "mem/tport.hh" 42#include "params/DMASequencer.hh" 43 44class AbstractController; 45 46struct DMARequest 47{ 48 uint64_t start_paddr; 49 int len; 50 bool write; 51 int bytes_completed; 52 int bytes_issued; 53 uint8_t *data; 54 PacketPtr pkt; 55}; 56 57class DMASequencer : public MemObject 58{ 59 public: 60 typedef DMASequencerParams Params; 61 DMASequencer(const Params *); 62 void init(); 63 64 public: 65 class MemSlavePort : public QueuedSlavePort 66 { 67 private: 68 SlavePacketQueue queue;
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