| 1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
|
1
2#ifndef DMASEQUENCER_H
3#define DMASEQUENCER_H
4
5#include <ostream>
6#include "mem/ruby/common/DataBlock.hh"
7#include "mem/ruby/system/RubyPort.hh"
8
9#include "params/DMASequencer.hh"
10
11struct DMARequest {
12 uint64_t start_paddr;
13 int len;
14 bool write;
15 int bytes_completed;
16 int bytes_issued;
17 uint8* data;
18 PacketPtr pkt;
19};
20
21class DMASequencer :public RubyPort {
22public:
23 typedef DMASequencerParams Params;
24 DMASequencer(const Params *);
25 void init();
26 /* external interface */
27 RequestStatus makeRequest(const RubyRequest & request);
28 bool busy() { return m_is_busy;}
29
30 /* SLICC callback */
31 void dataCallback(const DataBlock & dblk);
32 void ackCallback();
33
34 void printConfig(std::ostream & out);
35
36private:
37 void issueNext();
38
39private:
40 bool m_is_busy;
41 uint64_t m_data_block_mask;
42 DMARequest active_request;
43 int num_active_requests;
44};
45
46#endif // DMACONTROLLER_H
| 28
29#ifndef DMASEQUENCER_H
30#define DMASEQUENCER_H
31
32#include <ostream>
33#include "mem/ruby/common/DataBlock.hh"
34#include "mem/ruby/system/RubyPort.hh"
35
36#include "params/DMASequencer.hh"
37
38struct DMARequest {
39 uint64_t start_paddr;
40 int len;
41 bool write;
42 int bytes_completed;
43 int bytes_issued;
44 uint8* data;
45 PacketPtr pkt;
46};
47
48class DMASequencer :public RubyPort {
49public:
50 typedef DMASequencerParams Params;
51 DMASequencer(const Params *);
52 void init();
53 /* external interface */
54 RequestStatus makeRequest(const RubyRequest & request);
55 bool busy() { return m_is_busy;}
56
57 /* SLICC callback */
58 void dataCallback(const DataBlock & dblk);
59 void ackCallback();
60
61 void printConfig(std::ostream & out);
62
63private:
64 void issueNext();
65
66private:
67 bool m_is_busy;
68 uint64_t m_data_block_mask;
69 DMARequest active_request;
70 int num_active_requests;
71};
72
73#endif // DMACONTROLLER_H
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