1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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61 DMASequencer(const Params *);
62 void init();
63
64 public:
65 class MemSlavePort : public QueuedSlavePort
66 {
67 private:
68 SlavePacketQueue queue;
69 bool access_phys_mem;
70
71 public:
72 MemSlavePort(const std::string &_name, DMASequencer *_port,
73 bool _access_phys_mem, PortID id);
74 void hitCallback(PacketPtr pkt);
75 void evictionCallback(const Address& address);
76
77 protected:
78 bool recvTimingReq(PacketPtr pkt);
79
80 Tick recvAtomic(PacketPtr pkt)
81 { panic("DMASequencer::MemSlavePort::recvAtomic() not implemented!\n"); }

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135 bool m_usingRubyTester;
136
137 MemSlavePort slave_port;
138
139 DrainManager *drainManager;
140 System* system;
141
142 bool retry;
143 bool access_phys_mem;
144
145 bool m_is_busy;
146 uint64_t m_data_block_mask;
147 DMARequest active_request;
148};
149
150#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__