1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 */
28
29#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
31
32#include <memory>
33#include <ostream>
34
35#include "mem/protocol/DMASequencerRequestType.hh"
36#include "mem/ruby/common/DataBlock.hh"
37#include "mem/ruby/system/RubyPort.hh"
38#include "params/DMASequencer.hh"
39
40struct DMARequest
41{
42 uint64_t start_paddr;
43 int len;
44 bool write;
45 int bytes_completed;
46 int bytes_issued;
47 uint8_t *data;
48 PacketPtr pkt;
49};
50
51class DMASequencer : public RubyPort
52{
53 public:
54 typedef DMASequencerParams Params;
55 DMASequencer(const Params *);
56 void init() override;
57
58 /* external interface */
59 RequestStatus makeRequest(PacketPtr pkt);
60 bool busy() { return m_is_busy;}
61 int outstandingCount() const { return (m_is_busy ? 1 : 0); }
62 bool isDeadlockEventScheduled() const { return false; }
63 void descheduleDeadlockEvent() {}
64
65 /* SLICC callback */
66 void dataCallback(const DataBlock & dblk);
67 void ackCallback();
68
69 void recordRequestType(DMASequencerRequestType requestType);
70
71 private:
72 void issueNext();
73
74 bool m_is_busy;
75 uint64_t m_data_block_mask;
76 DMARequest active_request;
77};
78
79#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__