DMASequencer.cc (8232:b28d06a175be) DMASequencer.cc (8615:e66a566f2cfa)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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43DMASequencer::init()
44{
45 RubyPort::init();
46 m_is_busy = false;
47 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
48}
49
50RequestStatus
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 34 unchanged lines hidden (view full) ---

43DMASequencer::init()
44{
45 RubyPort::init();
46 m_is_busy = false;
47 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
48}
49
50RequestStatus
51DMASequencer::makeRequest(const RubyRequest &request)
51DMASequencer::makeRequest(PacketPtr pkt)
52{
53 if (m_is_busy) {
54 return RequestStatus_BufferFull;
55 }
56
52{
53 if (m_is_busy) {
54 return RequestStatus_BufferFull;
55 }
56
57 uint64_t paddr = request.m_PhysicalAddress.getAddress();
58 uint8_t* data = request.data;
59 int len = request.m_Size;
60 bool write = false;
61 switch(request.m_Type) {
62 case RubyRequestType_LD:
63 write = false;
64 break;
65 case RubyRequestType_ST:
66 write = true;
67 break;
68 default:
69 panic("DMASequencer::makeRequest does not support RubyRequestType");
70 return RequestStatus_NULL;
71 }
57 uint64_t paddr = pkt->getAddr();
58 uint8_t* data = pkt->getPtr<uint8_t>(true);
59 int len = pkt->getSize();
60 bool write = pkt->isWrite();
72
73 assert(!m_is_busy); // only support one outstanding DMA request
74 m_is_busy = true;
75
76 active_request.start_paddr = paddr;
77 active_request.write = write;
78 active_request.data = data;
79 active_request.len = len;
80 active_request.bytes_completed = 0;
81 active_request.bytes_issued = 0;
61
62 assert(!m_is_busy); // only support one outstanding DMA request
63 m_is_busy = true;
64
65 active_request.start_paddr = paddr;
66 active_request.write = write;
67 active_request.data = data;
68 active_request.len = len;
69 active_request.bytes_completed = 0;
70 active_request.bytes_issued = 0;
82 active_request.pkt = request.pkt;
71 active_request.pkt = pkt;
83
84 SequencerMsg *msg = new SequencerMsg;
85 msg->getPhysicalAddress() = Address(paddr);
86 msg->getLineAddress() = line_address(msg->getPhysicalAddress());
87 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
88 int offset = paddr & m_data_block_mask;
89
90 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?

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73 SequencerMsg *msg = new SequencerMsg;
74 msg->getPhysicalAddress() = Address(paddr);
75 msg->getLineAddress() = line_address(msg->getPhysicalAddress());
76 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
77 int offset = paddr & m_data_block_mask;
78
79 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?

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