DMASequencer.cc (7453:1a5db3dd0f62) DMASequencer.cc (7544:90c5eb6a5e66)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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44 RubyPort::init();
45 m_is_busy = false;
46 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
47}
48
49RequestStatus
50DMASequencer::makeRequest(const RubyRequest &request)
51{
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 35 unchanged lines hidden (view full) ---

44 RubyPort::init();
45 m_is_busy = false;
46 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
47}
48
49RequestStatus
50DMASequencer::makeRequest(const RubyRequest &request)
51{
52 if (m_is_busy) {
53 return RequestStatus_BufferFull;
54 }
55
52 uint64_t paddr = request.paddr;
53 uint8_t* data = request.data;
54 int len = request.len;
55 bool write = false;
56 switch(request.type) {
57 case RubyRequestType_LD:
58 write = false;
59 break;

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103}
104
105void
106DMASequencer::issueNext()
107{
108 assert(m_is_busy == true);
109 active_request.bytes_completed = active_request.bytes_issued;
110 if (active_request.len == active_request.bytes_completed) {
56 uint64_t paddr = request.paddr;
57 uint8_t* data = request.data;
58 int len = request.len;
59 bool write = false;
60 switch(request.type) {
61 case RubyRequestType_LD:
62 write = false;
63 break;

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107}
108
109void
110DMASequencer::issueNext()
111{
112 assert(m_is_busy == true);
113 active_request.bytes_completed = active_request.bytes_issued;
114 if (active_request.len == active_request.bytes_completed) {
115 DPRINTF(RubyDma, "DMA request completed\n");
111 ruby_hit_callback(active_request.pkt);
112 m_is_busy = false;
113 return;
114 }
115
116 SequencerMsg *msg = new SequencerMsg;
117 msg->getPhysicalAddress() = Address(active_request.start_paddr +
118 active_request.bytes_completed);

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136 msg->getType() = SequencerRequestType_ST;
137 } else {
138 msg->getType() = SequencerRequestType_LD;
139 }
140
141 assert(m_mandatory_q_ptr != NULL);
142 m_mandatory_q_ptr->enqueue(msg);
143 active_request.bytes_issued += msg->getLen();
116 ruby_hit_callback(active_request.pkt);
117 m_is_busy = false;
118 return;
119 }
120
121 SequencerMsg *msg = new SequencerMsg;
122 msg->getPhysicalAddress() = Address(active_request.start_paddr +
123 active_request.bytes_completed);

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141 msg->getType() = SequencerRequestType_ST;
142 } else {
143 msg->getType() = SequencerRequestType_LD;
144 }
145
146 assert(m_mandatory_q_ptr != NULL);
147 m_mandatory_q_ptr->enqueue(msg);
148 active_request.bytes_issued += msg->getLen();
149 DPRINTF(RubyDma, "Next DMA segment issued to the DMA cntrl\n");
144}
145
146void
147DMASequencer::dataCallback(const DataBlock & dblk)
148{
149 assert(m_is_busy == true);
150 int len = active_request.bytes_issued - active_request.bytes_completed;
151 int offset = 0;

--- 24 unchanged lines hidden --- 		150}
151
152void
153DMASequencer::dataCallback(const DataBlock & dblk)
154{
155 assert(m_is_busy == true);
156 int len = active_request.bytes_issued - active_request.bytes_completed;
157 int offset = 0;

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