DMASequencer.cc (7008:90c097fb76e1) DMASequencer.cc (7039:bc0b6ea676b5)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "mem/ruby/system/DMASequencer.hh"
30#include "mem/ruby/buffers/MessageBuffer.hh"
31#include "mem/ruby/slicc_interface/AbstractController.hh"
32
33/* SLICC generated types */
34#include "mem/protocol/SequencerMsg.hh"
35#include "mem/protocol/SequencerRequestType.hh"
29#include "mem/protocol/SequencerMsg.hh"
30#include "mem/protocol/SequencerRequestType.hh"
31#include "mem/ruby/buffers/MessageBuffer.hh"
32#include "mem/ruby/slicc_interface/AbstractController.hh"
33#include "mem/ruby/system/DMASequencer.hh"
36#include "mem/ruby/system/System.hh"
37
34#include "mem/ruby/system/System.hh"
35
38//
39// Fix me: This code needs comments!
40//
41
42DMASequencer::DMASequencer(const Params *p)
36DMASequencer::DMASequencer(const Params *p)
43 : RubyPort(p)
37 : RubyPort(p)
44{
45}
46
38{
39}
40
47void DMASequencer::init()
41void
42DMASequencer::init()
48{
43{
49 RubyPort::init();
50 m_is_busy = false;
51 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
44 RubyPort::init();
45 m_is_busy = false;
46 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
52}
53
47}
48
54RequestStatus DMASequencer::makeRequest(const RubyRequest & request)
49RequestStatus
50DMASequencer::makeRequest(const RubyRequest &request)
55{
51{
56 uint64_t paddr = request.paddr;
57 uint8_t* data = request.data;
58 int len = request.len;
59 bool write = false;
60 switch(request.type) {
61 case RubyRequestType_LD:
62 write = false;
63 break;
64 case RubyRequestType_ST:
65 write = true;
66 break;
67 case RubyRequestType_NULL:
68 case RubyRequestType_IFETCH:
69 case RubyRequestType_Locked_Read:
70 case RubyRequestType_Locked_Write:
71 case RubyRequestType_RMW_Read:
72 case RubyRequestType_RMW_Write:
73 case RubyRequestType_NUM:
74 panic("DMASequencer::makeRequest does not support the RubyRequestType");
75 return RequestStatus_NULL;
76 }
52 uint64_t paddr = request.paddr;
53 uint8_t* data = request.data;
54 int len = request.len;
55 bool write = false;
56 switch(request.type) {
57 case RubyRequestType_LD:
58 write = false;
59 break;
60 case RubyRequestType_ST:
61 write = true;
62 break;
63 case RubyRequestType_NULL:
64 case RubyRequestType_IFETCH:
65 case RubyRequestType_Locked_Read:
66 case RubyRequestType_Locked_Write:
67 case RubyRequestType_RMW_Read:
68 case RubyRequestType_RMW_Write:
69 case RubyRequestType_NUM:
70 panic("DMASequencer::makeRequest does not support RubyRequestType");
71 return RequestStatus_NULL;
72 }
77
73
78 assert(!m_is_busy); // only support one outstanding DMA request
79 m_is_busy = true;
74 assert(!m_is_busy); // only support one outstanding DMA request
75 m_is_busy = true;
80
76
81 active_request.start_paddr = paddr;
82 active_request.write = write;
83 active_request.data = data;
84 active_request.len = len;
85 active_request.bytes_completed = 0;
86 active_request.bytes_issued = 0;
87 active_request.pkt = request.pkt;
77 active_request.start_paddr = paddr;
78 active_request.write = write;
79 active_request.data = data;
80 active_request.len = len;
81 active_request.bytes_completed = 0;
82 active_request.bytes_issued = 0;
83 active_request.pkt = request.pkt;
88
84
89 SequencerMsg msg;
90 msg.getPhysicalAddress() = Address(paddr);
91 msg.getLineAddress() = line_address(msg.getPhysicalAddress());
92 msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
93 int offset = paddr & m_data_block_mask;
85 SequencerMsg msg;
86 msg.getPhysicalAddress() = Address(paddr);
87 msg.getLineAddress() = line_address(msg.getPhysicalAddress());
88 msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
89 int offset = paddr & m_data_block_mask;
94
90
95 msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
96 len :
97 RubySystem::getBlockSizeBytes() - offset;
91 msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
92 len : RubySystem::getBlockSizeBytes() - offset;
98
93
99 if (write) {
100 msg.getDataBlk().setData(data, offset, msg.getLen());
101 }
94 if (write) {
95 msg.getDataBlk().setData(data, offset, msg.getLen());
96 }
102
97
103 assert(m_mandatory_q_ptr != NULL);
104 m_mandatory_q_ptr->enqueue(msg);
105 active_request.bytes_issued += msg.getLen();
98 assert(m_mandatory_q_ptr != NULL);
99 m_mandatory_q_ptr->enqueue(msg);
100 active_request.bytes_issued += msg.getLen();
106
101
107 return RequestStatus_Issued;
102 return RequestStatus_Issued;
108}
109
103}
104
110void DMASequencer::issueNext()
105void
106DMASequencer::issueNext()
111{
107{
112 assert(m_is_busy == true);
113 active_request.bytes_completed = active_request.bytes_issued;
114 if (active_request.len == active_request.bytes_completed) {
115 ruby_hit_callback(active_request.pkt);
116 m_is_busy = false;
117 return;
118 }
108 assert(m_is_busy == true);
109 active_request.bytes_completed = active_request.bytes_issued;
110 if (active_request.len == active_request.bytes_completed) {
111 ruby_hit_callback(active_request.pkt);
112 m_is_busy = false;
113 return;
114 }
119
115
120 SequencerMsg msg;
121 msg.getPhysicalAddress() = Address(active_request.start_paddr +
122 active_request.bytes_completed);
116 SequencerMsg msg;
117 msg.getPhysicalAddress() = Address(active_request.start_paddr +
118 active_request.bytes_completed);
123
119
124 assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
125 msg.getLineAddress() = line_address(msg.getPhysicalAddress());
120 assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
121 msg.getLineAddress() = line_address(msg.getPhysicalAddress());
126
122
127 msg.getType() = (active_request.write ? SequencerRequestType_ST :
128 SequencerRequestType_LD);
123 msg.getType() = (active_request.write ? SequencerRequestType_ST :
124 SequencerRequestType_LD);
129
125
130 msg.getLen() = (active_request.len -
131 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
132 active_request.len - active_request.bytes_completed :
133 RubySystem::getBlockSizeBytes());
126 msg.getLen() =
127 (active_request.len -
128 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
129 active_request.len - active_request.bytes_completed :
130 RubySystem::getBlockSizeBytes());
134
131
135 if (active_request.write) {
136 msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed],
137 0, msg.getLen());
138 msg.getType() = SequencerRequestType_ST;
139 } else {
140 msg.getType() = SequencerRequestType_LD;
141 }
132 if (active_request.write) {
133 msg.getDataBlk().
134 setData(&active_request.data[active_request.bytes_completed],
135 0, msg.getLen());
136 msg.getType() = SequencerRequestType_ST;
137 } else {
138 msg.getType() = SequencerRequestType_LD;
139 }
142
140
143 assert(m_mandatory_q_ptr != NULL);
144 m_mandatory_q_ptr->enqueue(msg);
145 active_request.bytes_issued += msg.getLen();
141 assert(m_mandatory_q_ptr != NULL);
142 m_mandatory_q_ptr->enqueue(msg);
143 active_request.bytes_issued += msg.getLen();
146}
147
144}
145
148void DMASequencer::dataCallback(const DataBlock & dblk)
146void
147DMASequencer::dataCallback(const DataBlock & dblk)
149{
148{
150 assert(m_is_busy == true);
151 int len = active_request.bytes_issued - active_request.bytes_completed;
152 int offset = 0;
153 if (active_request.bytes_completed == 0)
154 offset = active_request.start_paddr & m_data_block_mask;
155 assert( active_request.write == false );
156 memcpy(&active_request.data[active_request.bytes_completed],
157 dblk.getData(offset, len), len);
158 issueNext();
149 assert(m_is_busy == true);
150 int len = active_request.bytes_issued - active_request.bytes_completed;
151 int offset = 0;
152 if (active_request.bytes_completed == 0)
153 offset = active_request.start_paddr & m_data_block_mask;
154 assert(active_request.write == false);
155 memcpy(&active_request.data[active_request.bytes_completed],
156 dblk.getData(offset, len), len);
157 issueNext();
159}
160
158}
159
161void DMASequencer::ackCallback()
160void
161DMASequencer::ackCallback()
162{
162{
163 issueNext();
163 issueNext();
164}
165
164}
165
166void DMASequencer::printConfig(ostream & out)
166void
167DMASequencer::printConfig(ostream & out)
167{
168{
168
169}
170
169}
170
171
172DMASequencer *
173DMASequencerParams::create()
174{
175 return new DMASequencer(this);
176}
171DMASequencer *
172DMASequencerParams::create()
173{
174 return new DMASequencer(this);
175}