DMASequencer.cc (6888:de8e755aca4f) DMASequencer.cc (6922:1620cffaa3b6)
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/SequencerMsg.hh"
8#include "mem/protocol/SequencerRequestType.hh"

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19
20void DMASequencer::init()
21{
22 RubyPort::init();
23 m_is_busy = false;
24 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
25}
26
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/SequencerMsg.hh"
8#include "mem/protocol/SequencerRequestType.hh"

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19
20void DMASequencer::init()
21{
22 RubyPort::init();
23 m_is_busy = false;
24 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
25}
26
27int64_t DMASequencer::makeRequest(const RubyRequest & request)
27RequestStatus DMASequencer::makeRequest(const RubyRequest & request)
28{
29 uint64_t paddr = request.paddr;
30 uint8_t* data = request.data;
31 int len = request.len;
32 bool write = false;
33 switch(request.type) {
34 case RubyRequestType_LD:
35 write = false;
36 break;
37 case RubyRequestType_ST:
38 write = true;
39 break;
40 case RubyRequestType_NULL:
41 case RubyRequestType_IFETCH:
42 case RubyRequestType_Locked_Read:
43 case RubyRequestType_Locked_Write:
44 case RubyRequestType_RMW_Read:
45 case RubyRequestType_RMW_Write:
46 case RubyRequestType_NUM:
28{
29 uint64_t paddr = request.paddr;
30 uint8_t* data = request.data;
31 int len = request.len;
32 bool write = false;
33 switch(request.type) {
34 case RubyRequestType_LD:
35 write = false;
36 break;
37 case RubyRequestType_ST:
38 write = true;
39 break;
40 case RubyRequestType_NULL:
41 case RubyRequestType_IFETCH:
42 case RubyRequestType_Locked_Read:
43 case RubyRequestType_Locked_Write:
44 case RubyRequestType_RMW_Read:
45 case RubyRequestType_RMW_Write:
46 case RubyRequestType_NUM:
47 assert(0);
47 panic("DMASequencer::makeRequest does not support the RubyRequestType");
48 return RequestStatus_NULL;
48 }
49
50 assert(!m_is_busy); // only support one outstanding DMA request
51 m_is_busy = true;
52
53 active_request.start_paddr = paddr;
54 active_request.write = write;
55 active_request.data = data;
56 active_request.len = len;
57 active_request.bytes_completed = 0;
58 active_request.bytes_issued = 0;
49 }
50
51 assert(!m_is_busy); // only support one outstanding DMA request
52 m_is_busy = true;
53
54 active_request.start_paddr = paddr;
55 active_request.write = write;
56 active_request.data = data;
57 active_request.len = len;
58 active_request.bytes_completed = 0;
59 active_request.bytes_issued = 0;
59 active_request.id = makeUniqueRequestID();
60 active_request.pkt = request.pkt;
60
61 SequencerMsg msg;
62 msg.getPhysicalAddress() = Address(paddr);
63 msg.getLineAddress() = line_address(msg.getPhysicalAddress());
64 msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
65 int offset = paddr & m_data_block_mask;
66
67 msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
68 len :
69 RubySystem::getBlockSizeBytes() - offset;
70
71 if (write) {
72 msg.getDataBlk().setData(data, offset, msg.getLen());
73 }
74
75 assert(m_mandatory_q_ptr != NULL);
76 m_mandatory_q_ptr->enqueue(msg);
77 active_request.bytes_issued += msg.getLen();
78
61
62 SequencerMsg msg;
63 msg.getPhysicalAddress() = Address(paddr);
64 msg.getLineAddress() = line_address(msg.getPhysicalAddress());
65 msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
66 int offset = paddr & m_data_block_mask;
67
68 msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
69 len :
70 RubySystem::getBlockSizeBytes() - offset;
71
72 if (write) {
73 msg.getDataBlk().setData(data, offset, msg.getLen());
74 }
75
76 assert(m_mandatory_q_ptr != NULL);
77 m_mandatory_q_ptr->enqueue(msg);
78 active_request.bytes_issued += msg.getLen();
79
79 return active_request.id;
80 return RequestStatus_Issued;
80}
81
82void DMASequencer::issueNext()
83{
84 assert(m_is_busy == true);
85 active_request.bytes_completed = active_request.bytes_issued;
86 if (active_request.len == active_request.bytes_completed) {
81}
82
83void DMASequencer::issueNext()
84{
85 assert(m_is_busy == true);
86 active_request.bytes_completed = active_request.bytes_issued;
87 if (active_request.len == active_request.bytes_completed) {
87 m_hit_callback(active_request.id);
88 ruby_hit_callback(active_request.pkt);
88 m_is_busy = false;
89 return;
90 }
91
92 SequencerMsg msg;
93 msg.getPhysicalAddress() = Address(active_request.start_paddr +
89 m_is_busy = false;
90 return;
91 }
92
93 SequencerMsg msg;
94 msg.getPhysicalAddress() = Address(active_request.start_paddr +
94 active_request.bytes_completed);
95 active_request.bytes_completed);
95
96 assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
97 msg.getLineAddress() = line_address(msg.getPhysicalAddress());
98
99 msg.getType() = (active_request.write ? SequencerRequestType_ST :
100 SequencerRequestType_LD);
101
102 msg.getLen() = (active_request.len -

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97 assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
98 msg.getLineAddress() = line_address(msg.getPhysicalAddress());
99
100 msg.getType() = (active_request.write ? SequencerRequestType_ST :
101 SequencerRequestType_LD);
102
103 msg.getLen() = (active_request.len -

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