DMASequencer.cc (6369:82ac95f4d9f0) DMASequencer.cc (6433:0f0f0fbef977)
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/DMARequestMsg.hh"
8#include "mem/protocol/DMARequestType.hh"

--- 37 unchanged lines hidden (view full) ---

46 write = true;
47 break;
48 case RubyRequestType_NULL:
49 case RubyRequestType_IFETCH:
50 case RubyRequestType_Locked_Read:
51 case RubyRequestType_Locked_Write:
52 case RubyRequestType_RMW_Read:
53 case RubyRequestType_RMW_Write:
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/DMARequestMsg.hh"
8#include "mem/protocol/DMARequestType.hh"

--- 37 unchanged lines hidden (view full) ---

46 write = true;
47 break;
48 case RubyRequestType_NULL:
49 case RubyRequestType_IFETCH:
50 case RubyRequestType_Locked_Read:
51 case RubyRequestType_Locked_Write:
52 case RubyRequestType_RMW_Read:
53 case RubyRequestType_RMW_Write:
54 case RubyRequestType_NUM:
54 assert(0);
55 }
56
57 assert(!m_is_busy); // only support one outstanding DMA request
58 m_is_busy = true;
59
60 active_request.start_paddr = paddr;
61 active_request.write = write;

--- 81 unchanged lines hidden --- 		55 assert(0);
56 }
57
58 assert(!m_is_busy); // only support one outstanding DMA request
59 m_is_busy = true;
60
61 active_request.start_paddr = paddr;
62 active_request.write = write;

--- 81 unchanged lines hidden ---