DMASequencer.cc (6350:accdf59eedd3) DMASequencer.cc (6355:79464d8a4d2f)
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/DMARequestMsg.hh"
8#include "mem/protocol/DMARequestType.hh"

--- 34 unchanged lines hidden (view full) ---

43 break;
44 case RubyRequestType_ST:
45 write = true;
46 break;
47 case RubyRequestType_NULL:
48 case RubyRequestType_IFETCH:
49 case RubyRequestType_Locked_Read:
50 case RubyRequestType_Locked_Write:
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/DMARequestMsg.hh"
8#include "mem/protocol/DMARequestType.hh"

--- 34 unchanged lines hidden (view full) ---

43 break;
44 case RubyRequestType_ST:
45 write = true;
46 break;
47 case RubyRequestType_NULL:
48 case RubyRequestType_IFETCH:
49 case RubyRequestType_Locked_Read:
50 case RubyRequestType_Locked_Write:
51 case RubyRequestType_RMW_Read:
52 case RubyRequestType_RMW_Write:
51 assert(0);
52 }
53
54 assert(!m_is_busy);
55 m_is_busy = true;
56
57 active_request.start_paddr = paddr;
58 active_request.write = write;

--- 73 unchanged lines hidden --- 		53 assert(0);
54 }
55
56 assert(!m_is_busy);
57 m_is_busy = true;
58
59 active_request.start_paddr = paddr;
60 active_request.write = write;

--- 73 unchanged lines hidden ---