DMASequencer.cc (11111:6da33e720481) DMASequencer.cc (11284:b3926db25371)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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84
85bool
86DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
87{
88 DPRINTF(RubyDma, "Timing request for address %#x on port %d\n",
89 pkt->getAddr(), id);
90 DMASequencer *seq = static_cast<DMASequencer *>(&owner);
91
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 75 unchanged lines hidden (view full) ---

84
85bool
86DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
87{
88 DPRINTF(RubyDma, "Timing request for address %#x on port %d\n",
89 pkt->getAddr(), id);
90 DMASequencer *seq = static_cast<DMASequencer *>(&owner);
91
92 if (pkt->memInhibitAsserted())
93 panic("DMASequencer should never see an inhibited request\n");
92 if (pkt->cacheResponding())
93 panic("DMASequencer should never see a request with the "
94 "cacheResponding flag set\n");
94
95 assert(isPhysMemAddress(pkt->getAddr()));
96 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
97 RubySystem::getBlockSizeBytes());
98
99 // Submit the ruby request
100 RequestStatus requestStatus = seq->makeRequest(pkt);
101

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95
96 assert(isPhysMemAddress(pkt->getAddr()));
97 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
98 RubySystem::getBlockSizeBytes());
99
100 // Submit the ruby request
101 RequestStatus requestStatus = seq->makeRequest(pkt);
102

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