DMASequencer.cc (11108:6342ddf6d733) DMASequencer.cc (11111:6da33e720481)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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49}
50
51void
52DMASequencer::init()
53{
54 MemObject::init();
55 assert(m_controller != NULL);
56 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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49}
50
51void
52DMASequencer::init()
53{
54 MemObject::init();
55 assert(m_controller != NULL);
56 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
57 m_mandatory_q_ptr->setSender(this);
58 m_is_busy = false;
59 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
60
61 slave_port.sendRangeChange();
62}
63
64BaseSlavePort &
65DMASequencer::getSlavePort(const std::string &if_name, PortID idx)

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251
252 if (write && (data != NULL)) {
253 if (active_request.data != NULL) {
254 msg->getDataBlk().setData(data, offset, msg->getLen());
255 }
256 }
257
258 assert(m_mandatory_q_ptr != NULL);
57 m_is_busy = false;
58 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
59
60 slave_port.sendRangeChange();
61}
62
63BaseSlavePort &
64DMASequencer::getSlavePort(const std::string &if_name, PortID idx)

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250
251 if (write && (data != NULL)) {
252 if (active_request.data != NULL) {
253 msg->getDataBlk().setData(data, offset, msg->getLen());
254 }
255 }
256
257 assert(m_mandatory_q_ptr != NULL);
259 m_mandatory_q_ptr->enqueue(msg);
258 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
260 active_request.bytes_issued += msg->getLen();
261
262 return RequestStatus_Issued;
263}
264
265void
266DMASequencer::issueNext()
267{

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297
298 if (active_request.write) {
299 msg->getDataBlk().
300 setData(&active_request.data[active_request.bytes_completed],
301 0, msg->getLen());
302 }
303
304 assert(m_mandatory_q_ptr != NULL);
259 active_request.bytes_issued += msg->getLen();
260
261 return RequestStatus_Issued;
262}
263
264void
265DMASequencer::issueNext()
266{

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296
297 if (active_request.write) {
298 msg->getDataBlk().
299 setData(&active_request.data[active_request.bytes_completed],
300 0, msg->getLen());
301 }
302
303 assert(m_mandatory_q_ptr != NULL);
305 m_mandatory_q_ptr->enqueue(msg);
304 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
306 active_request.bytes_issued += msg->getLen();
307 DPRINTF(RubyDma,
308 "DMA request bytes issued %d, bytes completed %d, total len %d\n",
309 active_request.bytes_issued, active_request.bytes_completed,
310 active_request.len);
311}
312
313void

--- 33 unchanged lines hidden --- 		305 active_request.bytes_issued += msg->getLen();
306 DPRINTF(RubyDma,
307 "DMA request bytes issued %d, bytes completed %d, total len %d\n",
308 active_request.bytes_issued, active_request.bytes_completed,
309 active_request.len);
310}
311
312void

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