DMASequencer.cc (10917:c38f28fad4c3) DMASequencer.cc (10919:80069a602c83)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#include "debug/RubyDma.hh"
34#include "debug/RubyStats.hh"
35#include "mem/protocol/SequencerMsg.hh"
36#include "mem/ruby/system/DMASequencer.hh"
37#include "mem/ruby/system/System.hh"
38#include "sim/system.hh"
39
40DMASequencer::DMASequencer(const Params *p)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#include "debug/RubyDma.hh"
34#include "debug/RubyStats.hh"
35#include "mem/protocol/SequencerMsg.hh"
36#include "mem/ruby/system/DMASequencer.hh"
37#include "mem/ruby/system/System.hh"
38#include "sim/system.hh"
39
40DMASequencer::DMASequencer(const Params *p)
41 : MemObject(p), m_version(p->version), m_controller(NULL),
42 m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester),
41 : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
42 m_controller(NULL), m_mandatory_q_ptr(NULL),
43 m_usingRubyTester(p->using_ruby_tester),
43 slave_port(csprintf("%s.slave", name()), this, 0, p->ruby_system,
44 p->ruby_system->getAccessBackingStore()),
45 system(p->system), retry(false)
46{
47 assert(m_version != -1);
48}
49
50void

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72 return slave_port;
73 }
74}
75
76DMASequencer::MemSlavePort::MemSlavePort(const std::string &_name,
77 DMASequencer *_port, PortID id, RubySystem* _ruby_system,
78 bool _access_backing_store)
79 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
44 slave_port(csprintf("%s.slave", name()), this, 0, p->ruby_system,
45 p->ruby_system->getAccessBackingStore()),
46 system(p->system), retry(false)
47{
48 assert(m_version != -1);
49}
50
51void

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73 return slave_port;
74 }
75}
76
77DMASequencer::MemSlavePort::MemSlavePort(const std::string &_name,
78 DMASequencer *_port, PortID id, RubySystem* _ruby_system,
79 bool _access_backing_store)
80 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
80 ruby_system(_ruby_system), access_backing_store(_access_backing_store)
81 m_ruby_system(_ruby_system), access_backing_store(_access_backing_store)
81{
82 DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name);
83}
84
85bool
86DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
87{
88 DPRINTF(RubyDma, "Timing request for address %#x on port %d\n",

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185 assert(!pkt->isLLSC());
186 assert(!pkt->isFlush());
187
188 DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse);
189
190 // turn packet around to go back to requester if response expected
191
192 if (access_backing_store) {
82{
83 DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name);
84}
85
86bool
87DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
88{
89 DPRINTF(RubyDma, "Timing request for address %#x on port %d\n",

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186 assert(!pkt->isLLSC());
187 assert(!pkt->isFlush());
188
189 DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse);
190
191 // turn packet around to go back to requester if response expected
192
193 if (access_backing_store) {
193 ruby_system->getPhysMem()->access(pkt);
194 m_ruby_system->getPhysMem()->access(pkt);
194 } else if (needsResponse) {
195 pkt->makeResponse();
196 }
197
198 if (needsResponse) {
199 DPRINTF(RubyDma, "Sending packet back over port\n");
200 // send next cycle
195 } else if (needsResponse) {
196 pkt->makeResponse();
197 }
198
199 if (needsResponse) {
200 DPRINTF(RubyDma, "Sending packet back over port\n");
201 // send next cycle
201 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
202 DMASequencer *seq = static_cast<DMASequencer *>(&owner);
203 RubySystem *rs = seq->m_ruby_system;
204 schedTimingResp(pkt, curTick() + rs->clockPeriod());
202 } else {
203 delete pkt;
204 }
205
206 DPRINTF(RubyDma, "Hit callback done!\n");
207}
208
209bool

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206 delete pkt;
207 }
208
209 DPRINTF(RubyDma, "Hit callback done!\n");
210}
211
212bool

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