DMASequencer.cc (10519:7a3ad4b09ce4) DMASequencer.cc (10562:b99fdc295c34)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 221 unchanged lines hidden (view full) ---

230RequestStatus
231DMASequencer::makeRequest(PacketPtr pkt)
232{
233 if (m_is_busy) {
234 return RequestStatus_BufferFull;
235 }
236
237 uint64_t paddr = pkt->getAddr();
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 221 unchanged lines hidden (view full) ---

230RequestStatus
231DMASequencer::makeRequest(PacketPtr pkt)
232{
233 if (m_is_busy) {
234 return RequestStatus_BufferFull;
235 }
236
237 uint64_t paddr = pkt->getAddr();
238 uint8_t* data = pkt->getPtr<uint8_t>(true);
238 uint8_t* data = pkt->getPtr();
239 int len = pkt->getSize();
240 bool write = pkt->isWrite();
241
242 assert(!m_is_busy); // only support one outstanding DMA request
243 m_is_busy = true;
244
245 active_request.start_paddr = paddr;
246 active_request.write = write;

--- 114 unchanged lines hidden --- 		239 int len = pkt->getSize();
240 bool write = pkt->isWrite();
241
242 assert(!m_is_busy); // only support one outstanding DMA request
243 m_is_busy = true;
244
245 active_request.start_paddr = paddr;
246 active_request.write = write;

--- 114 unchanged lines hidden ---