DMASequencer.cc (10518:30e3715c9405) DMASequencer.cc (10519:7a3ad4b09ce4)
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "mem/protocol/SequencerMsg.hh"
36#include "mem/ruby/system/DMASequencer.hh"
37#include "mem/ruby/system/System.hh"
38#include "sim/system.hh"
39
40DMASequencer::DMASequencer(const Params *p)
41 : MemObject(p), m_version(p->version), m_controller(NULL),
42 m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester),
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "mem/protocol/SequencerMsg.hh"
36#include "mem/ruby/system/DMASequencer.hh"
37#include "mem/ruby/system/System.hh"
38#include "sim/system.hh"
39
40DMASequencer::DMASequencer(const Params *p)
41 : MemObject(p), m_version(p->version), m_controller(NULL),
42 m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester),
43 slave_port(csprintf("%s.slave", name()), this, access_phys_mem, 0),
44 drainManager(NULL), system(p->system), retry(false),
45 access_phys_mem(p->access_phys_mem)
43 slave_port(csprintf("%s.slave", name()), this, 0),
44 drainManager(NULL), system(p->system), retry(false)
46{
47 assert(m_version != -1);
48}
49
50void
51DMASequencer::init()
52{
53 MemObject::init();
54 assert(m_controller != NULL);
55 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
56 m_mandatory_q_ptr->setSender(this);
57 m_is_busy = false;
58 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
45{
46 assert(m_version != -1);
47}
48
49void
50DMASequencer::init()
51{
52 MemObject::init();
53 assert(m_controller != NULL);
54 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
55 m_mandatory_q_ptr->setSender(this);
56 m_is_busy = false;
57 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
58
59 slave_port.sendRangeChange();
59}
60
61BaseSlavePort &
62DMASequencer::getSlavePort(const std::string &if_name, PortID idx)
63{
64 // used by the CPUs to connect the caches to the interconnect, and
65 // for the x86 case also the interrupt master
66 if (if_name != "slave") {
67 // pass it along to our super class
68 return MemObject::getSlavePort(if_name, idx);
69 } else {
70 return slave_port;
71 }
72}
73
74DMASequencer::MemSlavePort::MemSlavePort(const std::string &_name,
60}
61
62BaseSlavePort &
63DMASequencer::getSlavePort(const std::string &if_name, PortID idx)
64{
65 // used by the CPUs to connect the caches to the interconnect, and
66 // for the x86 case also the interrupt master
67 if (if_name != "slave") {
68 // pass it along to our super class
69 return MemObject::getSlavePort(if_name, idx);
70 } else {
71 return slave_port;
72 }
73}
74
75DMASequencer::MemSlavePort::MemSlavePort(const std::string &_name,
75 DMASequencer *_port, bool _access_phys_mem, PortID id)
76 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
77 access_phys_mem(_access_phys_mem)
76 DMASequencer *_port, PortID id)
77 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this)
78{
79 DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name);
80}
81
82bool
83DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
84{
85 DPRINTF(RubyDma, "Timing request for address %#x on port %d\n",

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197 setDrainState(Drainable::Drained);
198 return child_drain_count;
199}
200
201void
202DMASequencer::MemSlavePort::hitCallback(PacketPtr pkt)
203{
204 bool needsResponse = pkt->needsResponse();
78{
79 DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name);
80}
81
82bool
83DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
84{
85 DPRINTF(RubyDma, "Timing request for address %#x on port %d\n",

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197 setDrainState(Drainable::Drained);
198 return child_drain_count;
199}
200
201void
202DMASequencer::MemSlavePort::hitCallback(PacketPtr pkt)
203{
204 bool needsResponse = pkt->needsResponse();
205 bool accessPhysMem = access_phys_mem;
206
207 assert(!pkt->isLLSC());
208 assert(!pkt->isFlush());
209
210 DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse);
211
205 assert(!pkt->isLLSC());
206 assert(!pkt->isFlush());
207
208 DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse);
209
212 if (accessPhysMem) {
213 DMASequencer *seq = static_cast<DMASequencer *>(&owner);
214 seq->system->getPhysMem().access(pkt);
215 } else if (needsResponse) {
216 pkt->makeResponse();
217 }
218
219 // turn packet around to go back to requester if response expected
220 if (needsResponse) {
210 // turn packet around to go back to requester if response expected
211 if (needsResponse) {
212 pkt->makeResponse();
221 DPRINTF(RubyDma, "Sending packet back over port\n");
222 // send next cycle
223 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
224 } else {
225 delete pkt;
226 }
213 DPRINTF(RubyDma, "Sending packet back over port\n");
214 // send next cycle
215 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
216 } else {
217 delete pkt;
218 }
219
227 DPRINTF(RubyDma, "Hit callback done!\n");
228}
229
230bool
231DMASequencer::MemSlavePort::isPhysMemAddress(Addr addr) const
232{
233 DMASequencer *seq = static_cast<DMASequencer *>(&owner);
234 return seq->system->isMemAddr(addr);

--- 133 unchanged lines hidden --- 		220 DPRINTF(RubyDma, "Hit callback done!\n");
221}
222
223bool
224DMASequencer::MemSlavePort::isPhysMemAddress(Addr addr) const
225{
226 DMASequencer *seq = static_cast<DMASequencer *>(&owner);
227 return seq->system->isMemAddr(addr);

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