1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
| 1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
|
36#include "mem/ruby/system/RubySystem.hh"
37
38DMARequest::DMARequest(uint64_t start_paddr, int len, bool write,
39 int bytes_completed, int bytes_issued, uint8_t *data,
40 PacketPtr pkt)
41 : start_paddr(start_paddr), len(len), write(write),
42 bytes_completed(bytes_completed), bytes_issued(bytes_issued), data(data),
43 pkt(pkt)
44{
45}
46
47DMASequencer::DMASequencer(const Params *p)
48 : RubyPort(p), m_outstanding_count(0),
49 m_max_outstanding_requests(p->max_outstanding_requests)
50{
51}
52
53void
54DMASequencer::init()
55{
56 RubyPort::init();
57 m_data_block_mask = mask(RubySystem::getBlockSizeBits());
58
59 for (const auto &s_port : slave_ports)
60 s_port->sendRangeChange();
61}
62
63RequestStatus
64DMASequencer::makeRequest(PacketPtr pkt)
65{
66 if (m_outstanding_count == m_max_outstanding_requests) {
67 return RequestStatus_BufferFull;
68 }
69
70 Addr paddr = pkt->getAddr();
71 uint8_t* data = pkt->getPtr<uint8_t>();
72 int len = pkt->getSize();
73 bool write = pkt->isWrite();
74
75 assert(m_outstanding_count < m_max_outstanding_requests);
76 Addr line_addr = makeLineAddress(paddr);
77 auto emplace_pair =
78 m_RequestTable.emplace(std::piecewise_construct,
79 std::forward_as_tuple(line_addr),
80 std::forward_as_tuple(paddr, len, write, 0,
81 0, data, pkt));
82 DMARequest& active_request = emplace_pair.first->second;
83
84 // This is pretty conservative. A regular Sequencer with a more beefy
85 // request table that can track multiple requests for a cache line should
86 // be used if a more aggressive policy is needed.
87 if (!emplace_pair.second) {
88 DPRINTF(RubyDma, "DMA aliased: addr %p, len %d\n", line_addr, len);
89 return RequestStatus_Aliased;
90 }
91
92 DPRINTF(RubyDma, "DMA req created: addr %p, len %d\n", line_addr, len);
93
94 std::shared_ptr<SequencerMsg> msg =
95 std::make_shared<SequencerMsg>(clockEdge());
96 msg->getPhysicalAddress() = paddr;
97 msg->getLineAddress() = line_addr;
98 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
99 int offset = paddr & m_data_block_mask;
100
101 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
102 len : RubySystem::getBlockSizeBytes() - offset;
103
104 if (write && (data != NULL)) {
105 if (active_request.data != NULL) {
106 msg->getDataBlk().setData(data, offset, msg->getLen());
107 }
108 }
109
110 m_outstanding_count++;
111
112 assert(m_mandatory_q_ptr != NULL);
113 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
114 active_request.bytes_issued += msg->getLen();
115
116 return RequestStatus_Issued;
117}
118
119void
120DMASequencer::issueNext(const Addr& address)
121{
122 RequestTable::iterator i = m_RequestTable.find(address);
123 assert(i != m_RequestTable.end());
124
125 DMARequest &active_request = i->second;
126
127 assert(m_outstanding_count <= m_max_outstanding_requests);
128 active_request.bytes_completed = active_request.bytes_issued;
129 if (active_request.len == active_request.bytes_completed) {
130 DPRINTF(RubyDma, "DMA request completed: addr %p, size %d\n",
131 address, active_request.len);
132 m_outstanding_count--;
133 PacketPtr pkt = active_request.pkt;
134 m_RequestTable.erase(i);
135 ruby_hit_callback(pkt);
136 return;
137 }
138
139 std::shared_ptr<SequencerMsg> msg =
140 std::make_shared<SequencerMsg>(clockEdge());
141 msg->getPhysicalAddress() = active_request.start_paddr +
142 active_request.bytes_completed;
143
144 assert((msg->getPhysicalAddress() & m_data_block_mask) == 0);
145 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
146
147 msg->getType() = (active_request.write ? SequencerRequestType_ST :
148 SequencerRequestType_LD);
149
150 msg->getLen() =
151 (active_request.len -
152 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
153 active_request.len - active_request.bytes_completed :
154 RubySystem::getBlockSizeBytes());
155
156 if (active_request.write) {
157 msg->getDataBlk().
158 setData(&active_request.data[active_request.bytes_completed],
159 0, msg->getLen());
160 }
161
162 assert(m_mandatory_q_ptr != NULL);
163 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
164 active_request.bytes_issued += msg->getLen();
165 DPRINTF(RubyDma,
166 "DMA request bytes issued %d, bytes completed %d, total len %d\n",
167 active_request.bytes_issued, active_request.bytes_completed,
168 active_request.len);
169}
170
171void
172DMASequencer::dataCallback(const DataBlock & dblk, const Addr& address)
173{
174
175 RequestTable::iterator i = m_RequestTable.find(address);
176 assert(i != m_RequestTable.end());
177
178 DMARequest &active_request = i->second;
179 int len = active_request.bytes_issued - active_request.bytes_completed;
180 int offset = 0;
181 if (active_request.bytes_completed == 0)
182 offset = active_request.start_paddr & m_data_block_mask;
183 assert(!active_request.write);
184 if (active_request.data != NULL) {
185 memcpy(&active_request.data[active_request.bytes_completed],
186 dblk.getData(offset, len), len);
187 }
188 issueNext(address);
189}
190
191void
192DMASequencer::ackCallback(const Addr& address)
193{
194 assert(m_RequestTable.find(address) != m_RequestTable.end());
195 issueNext(address);
196}
197
198void
199DMASequencer::recordRequestType(DMASequencerRequestType requestType)
200{
201 DPRINTF(RubyStats, "Recorded statistic: %s\n",
202 DMASequencerRequestType_to_string(requestType));
203}
204
205DMASequencer *
206DMASequencerParams::create()
207{
208 return new DMASequencer(this);
209}
| 37#include "mem/ruby/system/RubySystem.hh"
38
39DMARequest::DMARequest(uint64_t start_paddr, int len, bool write,
40 int bytes_completed, int bytes_issued, uint8_t *data,
41 PacketPtr pkt)
42 : start_paddr(start_paddr), len(len), write(write),
43 bytes_completed(bytes_completed), bytes_issued(bytes_issued), data(data),
44 pkt(pkt)
45{
46}
47
48DMASequencer::DMASequencer(const Params *p)
49 : RubyPort(p), m_outstanding_count(0),
50 m_max_outstanding_requests(p->max_outstanding_requests)
51{
52}
53
54void
55DMASequencer::init()
56{
57 RubyPort::init();
58 m_data_block_mask = mask(RubySystem::getBlockSizeBits());
59
60 for (const auto &s_port : slave_ports)
61 s_port->sendRangeChange();
62}
63
64RequestStatus
65DMASequencer::makeRequest(PacketPtr pkt)
66{
67 if (m_outstanding_count == m_max_outstanding_requests) {
68 return RequestStatus_BufferFull;
69 }
70
71 Addr paddr = pkt->getAddr();
72 uint8_t* data = pkt->getPtr<uint8_t>();
73 int len = pkt->getSize();
74 bool write = pkt->isWrite();
75
76 assert(m_outstanding_count < m_max_outstanding_requests);
77 Addr line_addr = makeLineAddress(paddr);
78 auto emplace_pair =
79 m_RequestTable.emplace(std::piecewise_construct,
80 std::forward_as_tuple(line_addr),
81 std::forward_as_tuple(paddr, len, write, 0,
82 0, data, pkt));
83 DMARequest& active_request = emplace_pair.first->second;
84
85 // This is pretty conservative. A regular Sequencer with a more beefy
86 // request table that can track multiple requests for a cache line should
87 // be used if a more aggressive policy is needed.
88 if (!emplace_pair.second) {
89 DPRINTF(RubyDma, "DMA aliased: addr %p, len %d\n", line_addr, len);
90 return RequestStatus_Aliased;
91 }
92
93 DPRINTF(RubyDma, "DMA req created: addr %p, len %d\n", line_addr, len);
94
95 std::shared_ptr<SequencerMsg> msg =
96 std::make_shared<SequencerMsg>(clockEdge());
97 msg->getPhysicalAddress() = paddr;
98 msg->getLineAddress() = line_addr;
99 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
100 int offset = paddr & m_data_block_mask;
101
102 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
103 len : RubySystem::getBlockSizeBytes() - offset;
104
105 if (write && (data != NULL)) {
106 if (active_request.data != NULL) {
107 msg->getDataBlk().setData(data, offset, msg->getLen());
108 }
109 }
110
111 m_outstanding_count++;
112
113 assert(m_mandatory_q_ptr != NULL);
114 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
115 active_request.bytes_issued += msg->getLen();
116
117 return RequestStatus_Issued;
118}
119
120void
121DMASequencer::issueNext(const Addr& address)
122{
123 RequestTable::iterator i = m_RequestTable.find(address);
124 assert(i != m_RequestTable.end());
125
126 DMARequest &active_request = i->second;
127
128 assert(m_outstanding_count <= m_max_outstanding_requests);
129 active_request.bytes_completed = active_request.bytes_issued;
130 if (active_request.len == active_request.bytes_completed) {
131 DPRINTF(RubyDma, "DMA request completed: addr %p, size %d\n",
132 address, active_request.len);
133 m_outstanding_count--;
134 PacketPtr pkt = active_request.pkt;
135 m_RequestTable.erase(i);
136 ruby_hit_callback(pkt);
137 return;
138 }
139
140 std::shared_ptr<SequencerMsg> msg =
141 std::make_shared<SequencerMsg>(clockEdge());
142 msg->getPhysicalAddress() = active_request.start_paddr +
143 active_request.bytes_completed;
144
145 assert((msg->getPhysicalAddress() & m_data_block_mask) == 0);
146 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
147
148 msg->getType() = (active_request.write ? SequencerRequestType_ST :
149 SequencerRequestType_LD);
150
151 msg->getLen() =
152 (active_request.len -
153 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
154 active_request.len - active_request.bytes_completed :
155 RubySystem::getBlockSizeBytes());
156
157 if (active_request.write) {
158 msg->getDataBlk().
159 setData(&active_request.data[active_request.bytes_completed],
160 0, msg->getLen());
161 }
162
163 assert(m_mandatory_q_ptr != NULL);
164 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
165 active_request.bytes_issued += msg->getLen();
166 DPRINTF(RubyDma,
167 "DMA request bytes issued %d, bytes completed %d, total len %d\n",
168 active_request.bytes_issued, active_request.bytes_completed,
169 active_request.len);
170}
171
172void
173DMASequencer::dataCallback(const DataBlock & dblk, const Addr& address)
174{
175
176 RequestTable::iterator i = m_RequestTable.find(address);
177 assert(i != m_RequestTable.end());
178
179 DMARequest &active_request = i->second;
180 int len = active_request.bytes_issued - active_request.bytes_completed;
181 int offset = 0;
182 if (active_request.bytes_completed == 0)
183 offset = active_request.start_paddr & m_data_block_mask;
184 assert(!active_request.write);
185 if (active_request.data != NULL) {
186 memcpy(&active_request.data[active_request.bytes_completed],
187 dblk.getData(offset, len), len);
188 }
189 issueNext(address);
190}
191
192void
193DMASequencer::ackCallback(const Addr& address)
194{
195 assert(m_RequestTable.find(address) != m_RequestTable.end());
196 issueNext(address);
197}
198
199void
200DMASequencer::recordRequestType(DMASequencerRequestType requestType)
201{
202 DPRINTF(RubyStats, "Recorded statistic: %s\n",
203 DMASequencerRequestType_to_string(requestType));
204}
205
206DMASequencer *
207DMASequencerParams::create()
208{
209 return new DMASequencer(this);
210}
|