1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <memory> 30 31#include "debug/RubyDma.hh" 32#include "debug/RubyStats.hh" 33#include "mem/protocol/SequencerMsg.hh" 34#include "mem/protocol/SequencerRequestType.hh" 35#include "mem/ruby/system/DMASequencer.hh" 36#include "mem/ruby/system/RubySystem.hh" 37
| 1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <memory> 30 31#include "debug/RubyDma.hh" 32#include "debug/RubyStats.hh" 33#include "mem/protocol/SequencerMsg.hh" 34#include "mem/protocol/SequencerRequestType.hh" 35#include "mem/ruby/system/DMASequencer.hh" 36#include "mem/ruby/system/RubySystem.hh" 37
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| 38DMARequest::DMARequest(uint64_t start_paddr, int len, bool write, 39 int bytes_completed, int bytes_issued, uint8_t *data, 40 PacketPtr pkt) 41 : start_paddr(start_paddr), len(len), write(write), 42 bytes_completed(bytes_completed), bytes_issued(bytes_issued), data(data), 43 pkt(pkt) 44{ 45} 46
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38DMASequencer::DMASequencer(const Params *p)
| 47DMASequencer::DMASequencer(const Params *p)
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39 : RubyPort(p)
| 48 : RubyPort(p), m_outstanding_count(0), 49 m_max_outstanding_requests(p->max_outstanding_requests)
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40{ 41} 42 43void 44DMASequencer::init() 45{ 46 RubyPort::init();
| 50{ 51} 52 53void 54DMASequencer::init() 55{ 56 RubyPort::init();
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47 m_is_busy = false;
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48 m_data_block_mask = mask(RubySystem::getBlockSizeBits()); 49 50 for (const auto &s_port : slave_ports) 51 s_port->sendRangeChange(); 52} 53 54RequestStatus 55DMASequencer::makeRequest(PacketPtr pkt) 56{
| 57 m_data_block_mask = mask(RubySystem::getBlockSizeBits()); 58 59 for (const auto &s_port : slave_ports) 60 s_port->sendRangeChange(); 61} 62 63RequestStatus 64DMASequencer::makeRequest(PacketPtr pkt) 65{
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57 if (m_is_busy) {
| 66 if (m_outstanding_count == m_max_outstanding_requests) {
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58 return RequestStatus_BufferFull; 59 } 60 61 Addr paddr = pkt->getAddr(); 62 uint8_t* data = pkt->getPtr<uint8_t>(); 63 int len = pkt->getSize(); 64 bool write = pkt->isWrite(); 65
| 67 return RequestStatus_BufferFull; 68 } 69 70 Addr paddr = pkt->getAddr(); 71 uint8_t* data = pkt->getPtr<uint8_t>(); 72 int len = pkt->getSize(); 73 bool write = pkt->isWrite(); 74
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66 assert(!m_is_busy); // only support one outstanding DMA request 67 m_is_busy = true;
| 75 assert(m_outstanding_count < m_max_outstanding_requests); 76 Addr line_addr = makeLineAddress(paddr); 77 auto emplace_pair = 78 m_RequestTable.emplace(std::piecewise_construct, 79 std::forward_as_tuple(line_addr), 80 std::forward_as_tuple(paddr, len, write, 0, 81 0, data, pkt)); 82 DMARequest& active_request = emplace_pair.first->second;
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68
| 83
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69 active_request.start_paddr = paddr; 70 active_request.write = write; 71 active_request.data = data; 72 active_request.len = len; 73 active_request.bytes_completed = 0; 74 active_request.bytes_issued = 0; 75 active_request.pkt = pkt;
| 84 // This is pretty conservative. A regular Sequencer with a more beefy 85 // request table that can track multiple requests for a cache line should 86 // be used if a more aggressive policy is needed. 87 if (!emplace_pair.second) { 88 DPRINTF(RubyDma, "DMA aliased: addr %p, len %d\n", line_addr, len); 89 return RequestStatus_Aliased; 90 }
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76
| 91
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| 92 DPRINTF(RubyDma, "DMA req created: addr %p, len %d\n", line_addr, len); 93
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77 std::shared_ptr<SequencerMsg> msg = 78 std::make_shared<SequencerMsg>(clockEdge()); 79 msg->getPhysicalAddress() = paddr;
| 94 std::shared_ptr<SequencerMsg> msg = 95 std::make_shared<SequencerMsg>(clockEdge()); 96 msg->getPhysicalAddress() = paddr;
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80 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
| 97 msg->getLineAddress() = line_addr;
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81 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 82 int offset = paddr & m_data_block_mask; 83 84 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 85 len : RubySystem::getBlockSizeBytes() - offset; 86 87 if (write && (data != NULL)) { 88 if (active_request.data != NULL) { 89 msg->getDataBlk().setData(data, offset, msg->getLen()); 90 } 91 } 92
| 98 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 99 int offset = paddr & m_data_block_mask; 100 101 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 102 len : RubySystem::getBlockSizeBytes() - offset; 103 104 if (write && (data != NULL)) { 105 if (active_request.data != NULL) { 106 msg->getDataBlk().setData(data, offset, msg->getLen()); 107 } 108 } 109
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| 110 m_outstanding_count++; 111
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93 assert(m_mandatory_q_ptr != NULL); 94 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 95 active_request.bytes_issued += msg->getLen(); 96 97 return RequestStatus_Issued; 98} 99 100void
| 112 assert(m_mandatory_q_ptr != NULL); 113 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 114 active_request.bytes_issued += msg->getLen(); 115 116 return RequestStatus_Issued; 117} 118 119void
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101DMASequencer::issueNext()
| 120DMASequencer::issueNext(const Addr& address)
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102{
| 121{
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103 assert(m_is_busy);
| 122 RequestTable::iterator i = m_RequestTable.find(address); 123 assert(i != m_RequestTable.end()); 124 125 DMARequest &active_request = i->second; 126 127 assert(m_outstanding_count <= m_max_outstanding_requests);
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104 active_request.bytes_completed = active_request.bytes_issued; 105 if (active_request.len == active_request.bytes_completed) {
| 128 active_request.bytes_completed = active_request.bytes_issued; 129 if (active_request.len == active_request.bytes_completed) {
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106 // 107 // Must unset the busy flag before calling back the dma port because 108 // the callback may cause a previously nacked request to be reissued 109 // 110 DPRINTF(RubyDma, "DMA request completed\n"); 111 m_is_busy = false; 112 ruby_hit_callback(active_request.pkt);
| 130 DPRINTF(RubyDma, "DMA request completed: addr %p, size %d\n", 131 address, active_request.len); 132 m_outstanding_count--; 133 PacketPtr pkt = active_request.pkt; 134 m_RequestTable.erase(i); 135 ruby_hit_callback(pkt);
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113 return; 114 } 115 116 std::shared_ptr<SequencerMsg> msg = 117 std::make_shared<SequencerMsg>(clockEdge()); 118 msg->getPhysicalAddress() = active_request.start_paddr + 119 active_request.bytes_completed; 120 121 assert((msg->getPhysicalAddress() & m_data_block_mask) == 0); 122 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 123 124 msg->getType() = (active_request.write ? SequencerRequestType_ST : 125 SequencerRequestType_LD); 126 127 msg->getLen() = 128 (active_request.len - 129 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 130 active_request.len - active_request.bytes_completed : 131 RubySystem::getBlockSizeBytes()); 132 133 if (active_request.write) { 134 msg->getDataBlk(). 135 setData(&active_request.data[active_request.bytes_completed], 136 0, msg->getLen()); 137 } 138 139 assert(m_mandatory_q_ptr != NULL); 140 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 141 active_request.bytes_issued += msg->getLen(); 142 DPRINTF(RubyDma, 143 "DMA request bytes issued %d, bytes completed %d, total len %d\n", 144 active_request.bytes_issued, active_request.bytes_completed, 145 active_request.len); 146} 147 148void
| 136 return; 137 } 138 139 std::shared_ptr<SequencerMsg> msg = 140 std::make_shared<SequencerMsg>(clockEdge()); 141 msg->getPhysicalAddress() = active_request.start_paddr + 142 active_request.bytes_completed; 143 144 assert((msg->getPhysicalAddress() & m_data_block_mask) == 0); 145 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 146 147 msg->getType() = (active_request.write ? SequencerRequestType_ST : 148 SequencerRequestType_LD); 149 150 msg->getLen() = 151 (active_request.len - 152 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 153 active_request.len - active_request.bytes_completed : 154 RubySystem::getBlockSizeBytes()); 155 156 if (active_request.write) { 157 msg->getDataBlk(). 158 setData(&active_request.data[active_request.bytes_completed], 159 0, msg->getLen()); 160 } 161 162 assert(m_mandatory_q_ptr != NULL); 163 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 164 active_request.bytes_issued += msg->getLen(); 165 DPRINTF(RubyDma, 166 "DMA request bytes issued %d, bytes completed %d, total len %d\n", 167 active_request.bytes_issued, active_request.bytes_completed, 168 active_request.len); 169} 170 171void
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149DMASequencer::dataCallback(const DataBlock & dblk)
| 172DMASequencer::dataCallback(const DataBlock & dblk, const Addr& address)
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150{
| 173{
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151 assert(m_is_busy);
| 174 175 RequestTable::iterator i = m_RequestTable.find(address); 176 assert(i != m_RequestTable.end()); 177 178 DMARequest &active_request = i->second;
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152 int len = active_request.bytes_issued - active_request.bytes_completed; 153 int offset = 0; 154 if (active_request.bytes_completed == 0) 155 offset = active_request.start_paddr & m_data_block_mask; 156 assert(!active_request.write); 157 if (active_request.data != NULL) { 158 memcpy(&active_request.data[active_request.bytes_completed], 159 dblk.getData(offset, len), len); 160 }
| 179 int len = active_request.bytes_issued - active_request.bytes_completed; 180 int offset = 0; 181 if (active_request.bytes_completed == 0) 182 offset = active_request.start_paddr & m_data_block_mask; 183 assert(!active_request.write); 184 if (active_request.data != NULL) { 185 memcpy(&active_request.data[active_request.bytes_completed], 186 dblk.getData(offset, len), len); 187 }
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161 issueNext();
| 188 issueNext(address);
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162} 163 164void
| 189} 190 191void
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165DMASequencer::ackCallback()
| 192DMASequencer::ackCallback(const Addr& address)
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166{
| 193{
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167 issueNext();
| 194 RequestTable::iterator i = m_RequestTable.find(address); 195 assert(i != m_RequestTable.end()); 196 197 issueNext(address);
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168} 169 170void 171DMASequencer::recordRequestType(DMASequencerRequestType requestType) 172{ 173 DPRINTF(RubyStats, "Recorded statistic: %s\n", 174 DMASequencerRequestType_to_string(requestType)); 175} 176 177DMASequencer * 178DMASequencerParams::create() 179{ 180 return new DMASequencer(this); 181}
| 198} 199 200void 201DMASequencer::recordRequestType(DMASequencerRequestType requestType) 202{ 203 DPRINTF(RubyStats, "Recorded statistic: %s\n", 204 DMASequencerRequestType_to_string(requestType)); 205} 206 207DMASequencer * 208DMASequencerParams::create() 209{ 210 return new DMASequencer(this); 211}
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