CacheMemory.hh (11034:a89984ca7d15) CacheMemory.hh (11049:dfb0aa3f0649)
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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51{
52 public:
53 typedef RubyCacheParams Params;
54 CacheMemory(const Params *p);
55 ~CacheMemory();
56
57 void init();
58
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 42 unchanged lines hidden (view full) ---

51{
52 public:
53 typedef RubyCacheParams Params;
54 CacheMemory(const Params *p);
55 ~CacheMemory();
56
57 void init();
58
59 // Public Methods
60 // perform a cache access and see if we hit or not. Return true on a hit.
61 bool tryCacheAccess(Addr address, RubyRequestType type,
62 DataBlock*& data_ptr);
63
64 // similar to above, but doesn't require full access check
65 bool testCacheAccess(Addr address, RubyRequestType type,
66 DataBlock*& data_ptr);
67
59 // tests to see if an address is present in the cache
60 bool isTagPresent(Addr address) const;
61
62 // Returns true if there is:
63 // a) a tag match on this address or there is
64 // b) an unused line in the same cache "way"
65 bool cacheAvail(Addr address) const;
66

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84
85 // looks an address up in the cache
86 AbstractCacheEntry* lookup(Addr address);
87 const AbstractCacheEntry* lookup(Addr address) const;
88
89 Cycles getTagLatency() const { return tagArray.getLatency(); }
90 Cycles getDataLatency() const { return dataArray.getLatency(); }
91
68 // tests to see if an address is present in the cache
69 bool isTagPresent(Addr address) const;
70
71 // Returns true if there is:
72 // a) a tag match on this address or there is
73 // b) an unused line in the same cache "way"
74 bool cacheAvail(Addr address) const;
75

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93
94 // looks an address up in the cache
95 AbstractCacheEntry* lookup(Addr address);
96 const AbstractCacheEntry* lookup(Addr address) const;
97
98 Cycles getTagLatency() const { return tagArray.getLatency(); }
99 Cycles getDataLatency() const { return dataArray.getLatency(); }
100
92 bool isBlockInvalid(int64_t cache_set, int64_t loc);
93 bool isBlockNotBusy(int64_t cache_set, int64_t loc);
101 bool isBlockInvalid(int64 cache_set, int64 loc);
102 bool isBlockNotBusy(int64 cache_set, int64 loc);
94
95 // Hook for checkpointing the contents of the cache
96 void recordCacheContents(int cntrl, CacheRecorder* tr) const;
97
98 // Set this address to most recently used
99 void setMRU(Addr address);
103
104 // Hook for checkpointing the contents of the cache
105 void recordCacheContents(int cntrl, CacheRecorder* tr) const;
106
107 // Set this address to most recently used
108 void setMRU(Addr address);
100 // Set this entry to most recently used
101 void setMRU(const AbstractCacheEntry *e);
102
109
103 // Functions for locking and unlocking cache lines corresponding to the
104 // provided address. These are required for supporting atomic memory
105 // accesses. These are to be used when only the address of the cache entry
106 // is available. In case the entry itself is available. use the functions
107 // provided by the AbstractCacheEntry class.
108 void setLocked (Addr addr, int context);
109 void clearLocked (Addr addr);
110 bool isLocked (Addr addr, int context);
111
112 // Print cache contents
113 void print(std::ostream& out) const;
114 void printData(std::ostream& out) const;
115

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137 Stats::Scalar numDataArrayStalls;
138
139 int getCacheSize() const { return m_cache_size; }
140 int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
141 Addr getAddressAtIdx(int idx) const;
142
143 private:
144 // convert a Address to its location in the cache
110 void setLocked (Addr addr, int context);
111 void clearLocked (Addr addr);
112 bool isLocked (Addr addr, int context);
113
114 // Print cache contents
115 void print(std::ostream& out) const;
116 void printData(std::ostream& out) const;
117

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139 Stats::Scalar numDataArrayStalls;
140
141 int getCacheSize() const { return m_cache_size; }
142 int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
143 Addr getAddressAtIdx(int idx) const;
144
145 private:
146 // convert a Address to its location in the cache
145 int64_t addressToCacheSet(Addr address) const;
147 int64 addressToCacheSet(Addr address) const;
146
147 // Given a cache tag: returns the index of the tag in a set.
148 // returns -1 if the tag is not found.
148
149 // Given a cache tag: returns the index of the tag in a set.
150 // returns -1 if the tag is not found.
149 int findTagInSet(int64_t line, Addr tag) const;
150 int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const;
151 int findTagInSet(int64 line, Addr tag) const;
152 int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const;
151
152 // Private copy constructor and assignment operator
153 CacheMemory(const CacheMemory& obj);
154 CacheMemory& operator=(const CacheMemory& obj);
155
156 private:
157 // Data Members (m_prefix)
158 bool m_is_instruction_only_cache;

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154 // Private copy constructor and assignment operator
155 CacheMemory(const CacheMemory& obj);
156 CacheMemory& operator=(const CacheMemory& obj);
157
158 private:
159 // Data Members (m_prefix)
160 bool m_is_instruction_only_cache;

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