CacheMemory.hh (10980:7de6f95a0817) CacheMemory.hh (11019:fc1e41e88fd3)
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 82 unchanged lines hidden (view full) ---

91
92 // Returns with the physical address of the conflicting cache line
93 Address cacheProbe(const Address& address) const;
94
95 // looks an address up in the cache
96 AbstractCacheEntry* lookup(const Address& address);
97 const AbstractCacheEntry* lookup(const Address& address) const;
98
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 82 unchanged lines hidden (view full) ---

91
92 // Returns with the physical address of the conflicting cache line
93 Address cacheProbe(const Address& address) const;
94
95 // looks an address up in the cache
96 AbstractCacheEntry* lookup(const Address& address);
97 const AbstractCacheEntry* lookup(const Address& address) const;
98
99 Cycles getLatency() const { return m_latency; }
100 Cycles getTagLatency() const { return tagArray.getLatency(); }
101 Cycles getDataLatency() const { return dataArray.getLatency(); }
102
103 bool isBlockInvalid(int64 cache_set, int64 loc);
104 bool isBlockNotBusy(int64 cache_set, int64 loc);
105
106 // Hook for checkpointing the contents of the cache
107 void recordCacheContents(int cntrl, CacheRecorder* tr) const;

--- 46 unchanged lines hidden (view full) ---

154 int findTagInSetIgnorePermissions(int64 cacheSet,
155 const Address& tag) const;
156
157 // Private copy constructor and assignment operator
158 CacheMemory(const CacheMemory& obj);
159 CacheMemory& operator=(const CacheMemory& obj);
160
161 private:
99 Cycles getTagLatency() const { return tagArray.getLatency(); }
100 Cycles getDataLatency() const { return dataArray.getLatency(); }
101
102 bool isBlockInvalid(int64 cache_set, int64 loc);
103 bool isBlockNotBusy(int64 cache_set, int64 loc);
104
105 // Hook for checkpointing the contents of the cache
106 void recordCacheContents(int cntrl, CacheRecorder* tr) const;

--- 46 unchanged lines hidden (view full) ---

153 int findTagInSetIgnorePermissions(int64 cacheSet,
154 const Address& tag) const;
155
156 // Private copy constructor and assignment operator
157 CacheMemory(const CacheMemory& obj);
158 CacheMemory& operator=(const CacheMemory& obj);
159
160 private:
162 Cycles m_latency;
163
164 // Data Members (m_prefix)
165 bool m_is_instruction_only_cache;
166
167 // The first index is the # of cache lines.
168 // The second index is the the amount associativity.
169 m5::hash_map<Address, int> m_tag_index;
170 std::vector<std::vector<AbstractCacheEntry*> > m_cache;
171

--- 16 unchanged lines hidden --- 		161 // Data Members (m_prefix)
162 bool m_is_instruction_only_cache;
163
164 // The first index is the # of cache lines.
165 // The second index is the the amount associativity.
166 m5::hash_map<Address, int> m_tag_index;
167 std::vector<std::vector<AbstractCacheEntry*> > m_cache;
168

--- 16 unchanged lines hidden ---