1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
31#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
32
33#include <string>
34#include <vector>
35
36#include "base/hashmap.hh"
37#include "base/statistics.hh"
38#include "mem/protocol/CacheRequestType.hh"
39#include "mem/protocol/CacheResourceType.hh"
40#include "mem/protocol/RubyRequest.hh"
41#include "mem/ruby/common/DataBlock.hh"
42#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
43#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
44#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
45#include "mem/ruby/structures/BankedArray.hh"
46#include "mem/ruby/system/CacheRecorder.hh"
47#include "params/RubyCache.hh"
48#include "sim/sim_object.hh"
49
50class CacheMemory : public SimObject
51{
52 public:
53 typedef RubyCacheParams Params;
54 CacheMemory(const Params *p);
55 ~CacheMemory();
56
57 void init();
58
| 1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
31#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
32
33#include <string>
34#include <vector>
35
36#include "base/hashmap.hh"
37#include "base/statistics.hh"
38#include "mem/protocol/CacheRequestType.hh"
39#include "mem/protocol/CacheResourceType.hh"
40#include "mem/protocol/RubyRequest.hh"
41#include "mem/ruby/common/DataBlock.hh"
42#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
43#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
44#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
45#include "mem/ruby/structures/BankedArray.hh"
46#include "mem/ruby/system/CacheRecorder.hh"
47#include "params/RubyCache.hh"
48#include "sim/sim_object.hh"
49
50class CacheMemory : public SimObject
51{
52 public:
53 typedef RubyCacheParams Params;
54 CacheMemory(const Params *p);
55 ~CacheMemory();
56
57 void init();
58
|
| 59 // Public Methods
60 // perform a cache access and see if we hit or not. Return true on a hit.
61 bool tryCacheAccess(Addr address, RubyRequestType type,
62 DataBlock*& data_ptr);
63
64 // similar to above, but doesn't require full access check
65 bool testCacheAccess(Addr address, RubyRequestType type,
66 DataBlock*& data_ptr);
67
|
59 // tests to see if an address is present in the cache
60 bool isTagPresent(Addr address) const;
61
62 // Returns true if there is:
63 // a) a tag match on this address or there is
64 // b) an unused line in the same cache "way"
65 bool cacheAvail(Addr address) const;
66
67 // find an unused entry and sets the tag appropriate for the address
68 AbstractCacheEntry* allocate(Addr address,
69 AbstractCacheEntry* new_entry, bool touch);
70 AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry)
71 {
72 return allocate(address, new_entry, true);
73 }
74 void allocateVoid(Addr address, AbstractCacheEntry* new_entry)
75 {
76 allocate(address, new_entry, true);
77 }
78
79 // Explicitly free up this address
80 void deallocate(Addr address);
81
82 // Returns with the physical address of the conflicting cache line
83 Addr cacheProbe(Addr address) const;
84
85 // looks an address up in the cache
86 AbstractCacheEntry* lookup(Addr address);
87 const AbstractCacheEntry* lookup(Addr address) const;
88
89 Cycles getTagLatency() const { return tagArray.getLatency(); }
90 Cycles getDataLatency() const { return dataArray.getLatency(); }
91
| 68 // tests to see if an address is present in the cache
69 bool isTagPresent(Addr address) const;
70
71 // Returns true if there is:
72 // a) a tag match on this address or there is
73 // b) an unused line in the same cache "way"
74 bool cacheAvail(Addr address) const;
75
76 // find an unused entry and sets the tag appropriate for the address
77 AbstractCacheEntry* allocate(Addr address,
78 AbstractCacheEntry* new_entry, bool touch);
79 AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry)
80 {
81 return allocate(address, new_entry, true);
82 }
83 void allocateVoid(Addr address, AbstractCacheEntry* new_entry)
84 {
85 allocate(address, new_entry, true);
86 }
87
88 // Explicitly free up this address
89 void deallocate(Addr address);
90
91 // Returns with the physical address of the conflicting cache line
92 Addr cacheProbe(Addr address) const;
93
94 // looks an address up in the cache
95 AbstractCacheEntry* lookup(Addr address);
96 const AbstractCacheEntry* lookup(Addr address) const;
97
98 Cycles getTagLatency() const { return tagArray.getLatency(); }
99 Cycles getDataLatency() const { return dataArray.getLatency(); }
100
|
92 bool isBlockInvalid(int64_t cache_set, int64_t loc);
93 bool isBlockNotBusy(int64_t cache_set, int64_t loc);
| 101 bool isBlockInvalid(int64 cache_set, int64 loc);
102 bool isBlockNotBusy(int64 cache_set, int64 loc);
|
94
95 // Hook for checkpointing the contents of the cache
96 void recordCacheContents(int cntrl, CacheRecorder* tr) const;
97
98 // Set this address to most recently used
99 void setMRU(Addr address);
| 103
104 // Hook for checkpointing the contents of the cache
105 void recordCacheContents(int cntrl, CacheRecorder* tr) const;
106
107 // Set this address to most recently used
108 void setMRU(Addr address);
|
100 // Set this entry to most recently used
101 void setMRU(const AbstractCacheEntry *e);
| |
102
| 109
|
103 // Functions for locking and unlocking cache lines corresponding to the
104 // provided address. These are required for supporting atomic memory
105 // accesses. These are to be used when only the address of the cache entry
106 // is available. In case the entry itself is available. use the functions
107 // provided by the AbstractCacheEntry class.
| |
108 void setLocked (Addr addr, int context);
109 void clearLocked (Addr addr);
110 bool isLocked (Addr addr, int context);
111
112 // Print cache contents
113 void print(std::ostream& out) const;
114 void printData(std::ostream& out) const;
115
116 void regStats();
117 bool checkResourceAvailable(CacheResourceType res, Addr addr);
118 void recordRequestType(CacheRequestType requestType, Addr addr);
119
120 public:
121 Stats::Scalar m_demand_hits;
122 Stats::Scalar m_demand_misses;
123 Stats::Formula m_demand_accesses;
124
125 Stats::Scalar m_sw_prefetches;
126 Stats::Scalar m_hw_prefetches;
127 Stats::Formula m_prefetches;
128
129 Stats::Vector m_accessModeType;
130
131 Stats::Scalar numDataArrayReads;
132 Stats::Scalar numDataArrayWrites;
133 Stats::Scalar numTagArrayReads;
134 Stats::Scalar numTagArrayWrites;
135
136 Stats::Scalar numTagArrayStalls;
137 Stats::Scalar numDataArrayStalls;
138
139 int getCacheSize() const { return m_cache_size; }
140 int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
141 Addr getAddressAtIdx(int idx) const;
142
143 private:
144 // convert a Address to its location in the cache
| 110 void setLocked (Addr addr, int context);
111 void clearLocked (Addr addr);
112 bool isLocked (Addr addr, int context);
113
114 // Print cache contents
115 void print(std::ostream& out) const;
116 void printData(std::ostream& out) const;
117
118 void regStats();
119 bool checkResourceAvailable(CacheResourceType res, Addr addr);
120 void recordRequestType(CacheRequestType requestType, Addr addr);
121
122 public:
123 Stats::Scalar m_demand_hits;
124 Stats::Scalar m_demand_misses;
125 Stats::Formula m_demand_accesses;
126
127 Stats::Scalar m_sw_prefetches;
128 Stats::Scalar m_hw_prefetches;
129 Stats::Formula m_prefetches;
130
131 Stats::Vector m_accessModeType;
132
133 Stats::Scalar numDataArrayReads;
134 Stats::Scalar numDataArrayWrites;
135 Stats::Scalar numTagArrayReads;
136 Stats::Scalar numTagArrayWrites;
137
138 Stats::Scalar numTagArrayStalls;
139 Stats::Scalar numDataArrayStalls;
140
141 int getCacheSize() const { return m_cache_size; }
142 int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
143 Addr getAddressAtIdx(int idx) const;
144
145 private:
146 // convert a Address to its location in the cache
|
145 int64_t addressToCacheSet(Addr address) const;
| 147 int64 addressToCacheSet(Addr address) const;
|
146
147 // Given a cache tag: returns the index of the tag in a set.
148 // returns -1 if the tag is not found.
| 148
149 // Given a cache tag: returns the index of the tag in a set.
150 // returns -1 if the tag is not found.
|
149 int findTagInSet(int64_t line, Addr tag) const;
150 int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const;
| 151 int findTagInSet(int64 line, Addr tag) const;
152 int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const;
|
151
152 // Private copy constructor and assignment operator
153 CacheMemory(const CacheMemory& obj);
154 CacheMemory& operator=(const CacheMemory& obj);
155
156 private:
157 // Data Members (m_prefix)
158 bool m_is_instruction_only_cache;
159
160 // The first index is the # of cache lines.
161 // The second index is the the amount associativity.
162 m5::hash_map<Addr, int> m_tag_index;
163 std::vector<std::vector<AbstractCacheEntry*> > m_cache;
164
165 AbstractReplacementPolicy *m_replacementPolicy_ptr;
166
167 BankedArray dataArray;
168 BankedArray tagArray;
169
170 int m_cache_size;
171 int m_cache_num_sets;
172 int m_cache_num_set_bits;
173 int m_cache_assoc;
174 int m_start_index_bit;
175 bool m_resource_stalls;
176};
177
178std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
179
180#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
| 153
154 // Private copy constructor and assignment operator
155 CacheMemory(const CacheMemory& obj);
156 CacheMemory& operator=(const CacheMemory& obj);
157
158 private:
159 // Data Members (m_prefix)
160 bool m_is_instruction_only_cache;
161
162 // The first index is the # of cache lines.
163 // The second index is the the amount associativity.
164 m5::hash_map<Addr, int> m_tag_index;
165 std::vector<std::vector<AbstractCacheEntry*> > m_cache;
166
167 AbstractReplacementPolicy *m_replacementPolicy_ptr;
168
169 BankedArray dataArray;
170 BankedArray tagArray;
171
172 int m_cache_size;
173 int m_cache_num_sets;
174 int m_cache_num_set_bits;
175 int m_cache_assoc;
176 int m_start_index_bit;
177 bool m_resource_stalls;
178};
179
180std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
181
182#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
|